Research On High-Dependability Processor Architecture

With shrinking geometry, lower voltage and higher frequency, while gaining the improvedperformance the nanometer-scale processor becomes more sensitive and unreliable to thenoises due to crosstalk, power-jitter, electromagnetic interference and radiation, etc. At thesame time, in the harsh cosmic application the processor reliability is also a serious concernbecause of the single event effects caused by cosmic rays and high-energy particles.With godson-1 processor as the research prototype, a real chip developed by ICTCAS, thisdissertation deals with soft errors and focuses on research of high-dependability architecturefor nanometer-scale processor and harsh-application processor.The main innovative contributions of this dissertation include:1. A novel fast and continuous simulation-based fault injection technique is presented. Byrunning two synthesizable processor RTL models simultaneously, about thirty ten thousandsoft errors are injected into godson-1 successfully to direct the design of a fault-tolerantand dependable godson-1 processor with good statistical significance.2. An architectural low-cost fault-tolerant register technique is presented. Comparing withthe coarse method that all the processor registers are hardened roughly and blindly, theeconomical method that only the registers with 3% soft error sensitivity or above arehardened with the fault-tolerant register can achieve almost equal dependability whilereducing 81.9% register resources.3. A novel on-chip memory dependability technique based on locality is presented. Firstly,the access addresses are compared with the historical virtual address to keep the processormemory in idle state longer time. Secondly, a write-through-like strategy is further adoptedto keep data consistency between data Cache and main memory. With these two steps theon-chip memory becomes more reliable and can be protected with less efforts with only4.09% performance cost and 4.4% area cost.4. A static checking pipeline and selective re-execution technique is presented. By analyzingthe instructions and area ratios of different processor modules, a static pipeline is addedspecially to check the integrity for the ALU instructions, and all the fix-point multiply andfloat-point instructions are re-executed once for their integrity. By this technique all theinstructions integrity except for memory instructions can be checked with only 4.6% areacost and 2.93% performance cost.5. An exact resuming technique for pipeline timeout is presented. Four strategies for differentcases, including comparison with the added operation code in result bus, re-fetch andre-execution with a timeout exception, resetting the timeout-sensitive registers, TMR andECC, are introduced to bring the timeout processor back to normal state with only 0.5%area cost.6. An architectural fault-tolerant godson-1 processor is provided by this dissertation. Theabove-mentioned architectural fault-tolerant techniques are integrated into the godson-1synthesizable RTL model seamlessly only with total 7.22% performance cost and 9.8%area cost averagely.This dissertation is engaged in the research on high-dependability processor architectureand several novel architectural fault-tolerant techniques are presented. The research in thisdissertation is a significant exploration course for fault-tolerant and dependablenanometer-scale processor. And the practical fault-tolerant godson-1 processor can serve as anoptional high-dependability processor in the harsh cosmic application.