Research And Design Of 10GHz Spread Spectrum PLL

In the field of data transmission,the data interface between digital-to-analog converter ADC and field programmable gate array FPGA has been an engineering challenge.With the increasing sampling rate and resolution of digital-to-analog converter,the new JESD204B interface has replaced the traditional CMOS and LVDS interfaces for its higher speed transmission,less ports and wires.The design of key analog circuit in the JESD204B—PLL is a major difficulty.The PLL output clock signal provides a clock for the serializer in TX and clock data recovery circuit in RX.Low jitter clock will provide enough margin for both TX and RX of JESD204B,so the quality of the clock will directly affect the design difficulty of the entire JESD204B which is the key to ensure the stable operation of JESD204B.For a JESD204B interface circuit with a high-speed clock,the problems caused by EMI can not be ignored,it will interfere the normal transmission of communication data,and even lead to data errors.To prevent Electro Magnetic Interference(EMI),many methods have been proposed,such as shielding,separating,filtering circuits and clock spreading.Compared with shielding and other methods,clock spreading is to solve EMI problems from the source which can reduce development costs and risks,and is more flexible and more suitable for commercial needs.This thesis presents a 10GHz phase-locked loop for the 10Gbps rate JESD204B interface.The phase-locked loop is based on the classical type II charge pump PLL design,including the analog part—phase frequency detector,charge pump,filter,voltage controlled oscillator,oscillator buffer,prescaler and digital part—fractional divider.The non-ideal characteristics of each module of the PLL are analyzed and optimized.A mathematical model and a noise model are established to determine the filter parameters.The key module of the analog circuit—voltage controlled oscillator uses a pseudo differential secondary ring oscillator structure,the output frequency ranges from 7GHz to 12GHz and oscillator operates at 10 GHz when it has a tail current of 10 mA.The digital fractional divider uses phase delay compensation to reduce fractional spurs,and the key module phase interpolator has 32 levels high linear resolution with an accuracy up to 5%which can ensure the accuracy of fractional divider.The clock spread spectrum function is based on the fractional divider to prevent EMI.The spread-spectrum clock uses a triangle wave to modulate the fractional divider's instantaneous frequency division ratio.The modulation frequency is 31.5KHz and the modulation depth can be configured which can range from 500ppm to7500ppm.The proposed PLL is fabricated using tsmc55nm1P7M CMOS technology with a size of 0.088mm~2.The power consumption of PLL is 46.54mW.The test result shows PLL's RMS jitter is 630fs when the TX in JESD204B sends 10Gbps”0101”data,which meets the application requirements of JESD204B.Under 5000ppm clock spread,the energy suppression is 19.9dB which can effectively prevent EMI.