| With the rapid development of Internet information technology,network processing chips have more and more demand for high bandwidth interfaces.With the emergence of IP traffic explosion,and the emerging trends of software definition network(SDN)and OpenFlow,some co processors meet the needs of some mobile devices,data processing centers and enterprise individuals for high compatibility and efficient data processing.In order to facilitate data transmission of coprocessor and access devices,the chip manufacturers have defined the Interlaken LA protocol.Interlaken LA protocol is a new generation of high bandwidth packet transmission protocol applied to 40~100Gbps.The protocol is based on serial transmission technology,which makes the interconnection bandwidth of advanced communication equipment improved,using multiple serial links,establishing logical connection between devices and using multi channel,backvoltage capability and data integrity protection to improve the performance of communication devices.The Interlaken LA protocol has a great advantage in the transmission of data packets.The Interlaken LA protocol is a protocol for high bandwidth transmission,multichannel transmission and a flow control mechanism with data integrity.In this paper,the interface is designed according to the characteristics of Interlaken LA protocol.The design includes the transmitter and receiver of the interface,and the transmitter and receiver include frame layer and protocol layer.First,the simulated packets are sent to the protocol layer of the sending side,and the protocol layer treats 64 bit data as a Interlaken data word.The burst generation module of the sending protocol layer is responsible for generating incoming data.The burst control word carries information such as transmission,flow control,diagnosis,protocol type and application data block,which can be used to control the process of transmission and to ensure the correctness of data transmission.The sending end frame layer distribues the burst data generated by the protocol layer to the two layer transmission of the frame layer by striping.The frame generation module of the frame level transmitter is responsible for generating MetaFrame.The word boundary locking module of the receiver frame layer loclocks the word boundary on the incoming data,and then the meta frame locking solution scrambling module carries out the meta frame locking and scrambling code for the data.The strip alignment module is responsible for the alignment of the strip.The diagnostic module is responsible for the accuracy of incoming data.The interface transfers data through two bands,and the transfer end passes the data to the receiver through two and serial and serial parallel to parallel converter(Serial-Deserial,SerDes)SerDes interface.In order to build the interface verification platform,the transmitter and receiver transmit data using the SerDes channel implemented by the function code.The module realizes the word offset and strip offset in the SerDes transmission.Through the simulation,it is found that the frame layer sends out the sudden generation,the receiver completes the locking of the meta frame,and the scrambling code does not appear in the scrambling code,and the receiver realizes the strip alignment,and there is no error in the diagnosis of the data.Finally,after verification,the RTL interface code is synthesized by logic synthesis and physics synthesis.The JAZZ 180 nm process was adopted,and the layout area was 1591 um * 1085 um.The clock frequency of the interface is 253.3Mhz,and the data throughput is 16.21 Gbps. |
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