Optimization On Pipeline And Parallel Instruction Simulation Of TI C67X DSP

Instruction Set Simulator(ISS)is a software which runs on a host machine and can simulate another target computer.ISS can help develop and test applications,help design chips and help the co-design and co-development of software and hardware.Besides,as the hardware run faster and stronger,the demand for faster ISS is growing as well.In this paper,we analyzed the pipeline and parallel feature of TMS320C67x(called c67x from now on)architecture,the analysis and conclusion can be applied to other VLIW processors.Through analysis and experiment,we proposed two ISS optimization methods,the pipeline simulation optimization technique and parallel instructions destination registers lazy copy algorithm.Through experiments we found our methods can improve the performance significantly.Based on these techniques we build a c67x simulator,called sim6713.Our work was described below:1)To reduce the performance cost introduced by fully simulating all pipeline phases,we proposed a pipeline simulation optimization technique.By using a circular buffer to back up the destination registers and latency,we can only simulate the E1 phase of 10 phases of execution.Further,by analyzing large amounts of applications we found that all applications can have lots of nop instruction,and we proposed a nop instruction optimization technique.2)c67x processor has parallel feature,which allows at most 8 instructions being executed simultaneously.We proposed parallel instructions.destinationregisters lazy copy algorithm,which creates a copy of each destination register when simulating parallel instructions to hold the new value of the register and updates the original register after execute packet is finished.We found this approach can reduce large amounts of memory copying.3)We evaluated our simulator through extensive experiments,and found our optimization techniques can improve simulator performance significantly.