Schemes Design And Performance Analysis To Mitigate The Inter-cell Interference In Flash Memory

Recently,as a reprensentative Non-Volatile Storage,flash memory has got wide attention in the field of storage-data.Because of its efficient and reliable performance,flash memory has been obtained large-scale application and promotion in lots of scenarios.The rapid development of flash memory causes the requirements for data reliability of memory device are more and more urgent.The scaling down of cell size results in more serious interference in flash memory and makes inter-cell interference(ICI)as one of the dominant factors.This paper proposes two feasible schemes to solve the problems of ICI in flash memory.The main works are as follow:(1)This paper analysis essential cause of ICI noise and propose a novel scheme called pattern normalization(PN)based on the analysis of error patterns of ICI.In the PN scheme,a guards inserting(GI)method is proposed to insure that the PN scheme exerts good performance.By using the PN scheme,ICI is mitigated significantly.Integrating with PN scheme,the extraction of soft information for error-correcting coding(ECC)becomes simple.On the other hand,both horizontal and vertical ICI have been taken into account for the errors in flash memory.Through a series of simulations,we have analyzed the Bit Error Rate(BER)of system to demonstrate the effects of our schemes.(2)This paper also proposes a two-dimensional hierarchical constrained code(2D-HCC)to mitigate ICI of flash memory.Above proposed schemes is applied to both single-level cell(SLC)and multi-level cell(MLC)flash memory.Moreover,through simulating the flash memory system integrating above schemes with ECC such as LDPC codes and Bose-Chaudhuri-Hocquenghem(BCH)codes,we confirm the advantage of the proposed schemes.