Design Of Image Recognition System Based On Neural Network Accelerator

Computer Vision plays an important role in the field of industrial Internet of things.The most critical part of Computer Vision is image acquisition and image recognition algorithm.The Deep Convolution Neural Network algorithm has become the first choice for image recognition algrithms beceuse of its high recognition accuracy.In practical applications,the GPU is usually used to accelerate the neural network algorithm,but it consumes large power consumption,which limits its application in mobile embedded platforms with limited resources and power consumption.This thesis uses an all-programmable SoC embedded platform to design an image recognition system based on Convolution Neural Network Accelerator.The SoC is an ARM+FPGA architecture platform with features such as high performance,low power consumption,and rich programmable logic resources.The image recognition system designed in this thesis mainly includes an image acquisition system and a CNN accelerator.The image acquisition system achieves the image's acquisition and storage,and the maximum frame rate can be up to 30 fps.The CNN accelerator realizes the recognition of images by accelerating the forward prediction of the CNN algorithm.Because the CNN algorithm has the characteristics of high computational complexity and high memory access,increasing the degree of parallelism and data transmission bandwidth are the keys to the design of the accelerator.Based on the above ideas,this thesis designs a complete CNN accelerator,which mainly includes a dedicated computing unit,an instruction control unit,a storage control module,and an extended operation unit.In this thesis,32x7 fixed-point computational arrays and specific data paths are designed to increase the speed and memory bandwidth of the accelerators,while also reduces power consumption.For weight compression and sparseness of the netw ork,this thesis proposes a special storage method and designs a weighted address generation module to decompress compressed weights.For the disadvantage that the input data is low reuse when the step size is larger than 1,this thesis presents a method o f changing the step size of the input data sliding window to 1.This scheme can maximize the use of hardware parallelism and data path multiplexing,reduces the computation and the huge amount of input layer operation time and power consumption.This thesis finally uses the Xilinx Zynq-7060 development board to implement and verify the image recognition system.With the clock frequency of 100 Mhz,we uses trained pornographic image classification applications to this Accelerator.the Accelerator's calculation speed reaches 30 fps,and the power consumption is only 2.371 W.