Research And Implementation Of Graphical Hardware Description Language

In domestic and foreign colleges and universities,courses related to digital circuits have gradually turned to using graphical hardware description language(HDL)for circuit design,with Logisim and Digital as two main digital circuit designers and simulators.But Logisim and Digital can only be used as teaching tools.They only provide basic logic components to build a general circuit model.This does not meet the needs of industrial-grade CPUs and algorithm circuits,and it is impossible to design large-scale and efficient circuits.In addition,Logisim has long stopped maintenance due to its architecture,and Digital does not provide graphical support for the verification stage,which will lead developers to have to choose to learn the HDL.This paper is devoted to researching the technical route of graphical programming language.Based on Logisim hardware simulation language and Digital hardware description architecture,it explores how to add advanced features of graphical HDL to fill the gaps in the current graphical HDL.On this basis,this paper studies and implements the IP packaging methods and generic template of the graphical HDL,as well as the graphical Testbench.The goal of this paper is to realize the industrial-oriented design with the advanced features of the graphical HDL,and realize the graphical “zero programming” development from the design to the verification.The research work done in this paper is as follows.(1)Research on the IP packing and reference methods of graphical HDL.One is to pack the specific IP,so that the graphical design can embed the hardware resources of the FPGA chip(PLL/memory/peripheral)and make full use of the chip resources;the other is to reference the third-party Verilog code through the External component,which can reuse the huge accumulated Verilog resources in the past.(2)Research on the implementation of the generic mode of the graphical HDL and innovatively introduce the concept of generic in the high-level language into the graphical programming language,which will provide a more efficient design pattern for the iterative implementation of complex algorithm circuits.(3)Research on the implementation of graphical verification.By exploring the source code of Google Blockly and the characteristics of Verilog testbench,a graphical verification platform blockly TB has realized.Besides,further study the innovative implementation of blockly TB specific to Verilog testbench,providing a graphical programming solution for the circuit verification.(4)Develop Digiblock,a design platform with advanced features of graphical HDL.Digiblock integrates generic design,graphical IP resource,RISC-V assembly simulator RARS and graphical verification testbench blockly TB.Digiblock is a graphical digital circuit development platform that can meet industrial design.