Design And Implementation Of High Resolution Event Timer

High resolution event timing technology is used to accurately measure the time of event occurrence,which involves multi-disciplinary knowledge such as analog digital circuit,precise measuring instrument,high-speed signal processing,etc.It has a wide range of applications in various fields,such as laser ranging,laser imaging radar,satellite launch,long-distance satellite to ground time,navigation communication and positioning,high-speed signal testing instruments and many other aspects.This paper focuses on the research of high-resolution event timer.After scheme demonstration,hardware circuit simulation design,digital logic design,upper computer software programming and experimental verification,the design of high-resolution event timer with 5 ps LSB is realized,including:1.In this paper,the principle of high resolution time interval measurement based on TAC is analyzed,and the problems of slow measurement speed and obvious temperature drift are discussed.2.On the basis of the overall scheme,the selection of core devices is completed.The hardware circuit design adopts the modular design idea,mainly including comparator shaping module,logic control module,time interval measurement module,phase-locked clock module,self-tuning module,system status monitoring module and arm.According to different modules,the design idea is given.TAC circuit based on dual constant current source structure solves the problem of too long capacitance charge recovery time,and improves the measurement repetition rate on the premise of ensuring the measurement accuracy.3.The high-resolution timer system uses FPGA + ram architecture to achieve data acquisition,processing and transmission,in which FPGA and discrete components cooperate to achieve multi-channel independent measurement.The logic design adopts the top-down design principle,and divides the scheme into three modules: data acquisition and processing,data integration and communication.4.In order to further improve the accuracy and resolution of the system,the author has done the following three works: first,the circuit noise analysis and model simulation of TAC are carried out to guide the construction of low-noise circuit.Secondly,a self-tuning circuit and a correction algorithm are designed to eliminate the influence of ADC gain error and temperature drift.Finally,the phase-locked loop circuit is built to output high-quality clock signal on the premise of ensuring the reference clock and system clock phase synchronization.The final test results show that the RMS standard deviation is up to 3.6ps,and the timing repetition frequency is more than 2KHz.Key indicators meet the needs of the project.