RISC-V Processor Design And MCU Implementation Of Energy Metering

In 2019,State Grid put forward a concept of UEIOT(Ubiquitous Electric Internet of Things),and vigorously promoted constructions of UEIOT.Especially,the realization of information perception is the cornerstone of EUIOT constructions.As one of the critical sensing devices,smart meters play a very important role in the construction of UEIOT.Traditional meter MCUs are based on ARM Cortex M series processors,which are very efficient for controlling,but not tailored to processing calculations of energy metering.Therefore,this thesis designs a three-stage pipeline processor based on the RISCV instruction set architecture,which greatly improves efficiency of energy metering by defining new instructions.Compared with ARM Cortex-M series processors,the proposed processor has higher energy accumulation efficiency.In addition,the article also designs an interrupt controller module,a sleep and wake-up controller module and a debugging module,and integrates the three modules into a meter MCU.The specific functions of each module are as follows:(1)The interrupt controller module,managing 32 external interrupts with interrupt priority levels,and achieving interrupt nesting;(2)The sleep and wake-up controller module,controlling the MCU to enter or exit the low power working mode;(3)The debugging module,cooperating with the software to realize the halt,resume execution,single-step execution,hardware breakpoints,read and write registers and memory and other debugging functions.This design is implemented on Xilinx Kintex-7(xc7k410t-3fbg676)FPGA.The above functions are verified using a tool chain and debugging tools.The Core Mark score of the designed processor is 2.12 by running Core Mark program.