Risc Microcontroller Designs And Soc Integration Study

This paper introduced the design of a RISC MCU (Micro-Controller Unit) core. The verification of the design in FPGA device was fulfilled. The design and the verification of SOC (System on a Chip) based on RISC MCU core were also discussed in this paper.The RISC MCU core is compatible with PIC16C63A of Microchip at instruction set level. The RISC MCU architecture was analyzed in detail. The design of data path was also discussed. In the data path, many modules were designed and implemented, such as ALU. data bus unit, W(work register) and registers file. The designs of peripheral functional modules were finished, including USART, SPI and IO.The RISC MCU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-level instruction pipeline The performance of the RISC MCU has been improved by replacing micro-program with direct logic block. All the modules of RISC MCU core were described with Verilog HDL and synthesized with high-level synthesis EDA tools. Then the RISC MCU was implemented in FPGA device.The key technologies and methods for designing an integrated SOC(System on a Chip) are introduced in this paper. This paper gave the concept and design flow of software/hardware co-design and the principle of IP-reuse. The SOC on chip bus is analyzed in this paper. And we described how to design and verify a SOC design by a example, the design of a CAN bus node module. In this example we integrated the third party IP-CAN core with WISHBONE bus interface.This paper has contributed a lot to the design of the more complex RISC MCU. Simultaneously, it has given the way to the design of SOC based on MCU core.