Design Of Accelerator For SAW Echo Frequency Estimation Based On RISC-V

Passive wireless surface acoustic wave sensors(SAW)are very sensitive to changes in variables such as temperature,electric field,mass,force,etc.,making them increasingly popular in the Internet of Things and smart cities.Frequency estimation is one of the key techniques for estimating the echo signal of a surface acoustic wave sensor.It needs to solve the requirements of real-time and accuracy in the process of its realization.Among the various denoising algorithms currently available,the denoising algorithm based on singular value decomposition(SVD)has obvious effects and is easy to implement.In terms of echo frequency estimation,a fast frequency estimation algorithm based on Hartley transform is adopted,which improves the measurement accuracy and real-time performance compared with the FFT algorithm.With the development of large-scale integrated circuit design technology to this day,extremely low-power processors based on IoT applications are more demanding of low power consumption and low area.The current RISC-V architecture can avoid some complicated,lengthy and difficult-to-expandable architecture burdens,and supports modularity and customizable extensions,which can be applied to microprocessors in almost any field.Using the above advantages,the frequency estimation based on singular value decomposition filtering and Hartley transform is packaged into a private peripheral,and the SoC is connected through the private peripheral interface ICB bus.The ICB bus can be used in almost all occasions,including interfaces between internal modules,SRAM module interfaces,low-speed device buses,and system storage buses.This paper focuses on the key issues in the implementation of the SAW echo frequency estimation algorithm accelerator based on RISC-V.Specifically include the following aspects:(1)Introduce the flexibility and open architecture of RISC-V and the overall SAW system.From the perspective of feasibility,compare and study the advantages and disadvantages of various existing frequency estimation algorithms.Starting from time-frequency domain analysis and related processing methods,the reason for combining SVD filtering and FHT frequency estimation algorithm is put forward.(2)Analyze the specific problems in the implementation of the filtering algorithm based on SVD,convert the singular value decomposition of the matrix with the original data information into a real symmetric matrix,and then perform the singular value decomposition calculation,and use the parallel unilateral Jacobi calculation strategy to complete the matrix The diagonalization process reduces the complexity of the algorithm in actual calculations and speeds up the convergence.(3)Introduce the realization principle of the FHT(Fast Hartley Transform)algorithm in detail,and analyze the key links that affect the calculation efficiency,the algorithm complexity and the space complexity.And compared with FFT in speed and memory space saving.(4)Research on related algorithms and architecture design schemes based on SVD filtering and FHT calculation,design the related algorithm structure of Jacobi singular value decomposition suitable for this research and a series of memory space utilization and data flow calculation methods,and analyze the RISC-The key technology designed in the implementation process of V.At the same time,Matlab software is used to simulate the related algorithms,and the correctness of the timing simulation data pair is verified on VCS and Verdi.