Design And Implementation Of Lane Detection Accelerator Based On FPGA

With the rapid development of the national economy and the continuous improvement of infrastructure,cars are no longer a luxury for ordinary families.With more cars on the road,natural road traffic problems will also arise.In order to solve these problems effectively and reduce traffic accidents rate,the country has invested a lot of expenditure to support researchers studying intelligent connected vehicle.This direction has become a researching hotspot,and real-time lane detection is the basic task of realizing unmanned driving.It detects lane information and prepares for the lane deviation warning.However,there is no lane detection algorithm that can effectively deal with various complex road conditions at high speed.Therefore,how to improve the accuracy and real-time performance of lane detection on complex roads is a significant research direction.The Hough transform has been continuously improved to detect lane more accurately.Although the accuracy of the algorithm is improved,the time required for calculation becomes longer,and it cannot meet the real-time requirements.In order to achieve real-time goal,most of the current research on lane detection is concentrated on heterogeneous platforms of CPU + GPU.Due to the requirements of vehicle platform applications,witch need low power consumption and high cost performance,GPUs cost and power consumption are high,so it is not suitable for vehicle environments.However,with characteristic of programmable,low power consumption,and high concurrency,FPGA is very suitable for developing automotive scene applications.This essay chooses FPGA to design lane detection accelerator,the main content is as follows.1)A parallel strategy for improving Canny edge detection and histogram equalization based on FPGA.In this essay,histogram equalization is used to enhance the lane information of images with different light and dark levels,which makes the result of image preprocessing more conducive to subsequent detection.Considering the intensive features of histograms,using aggregated simulants to read multiple data at the same time for parallel processing to improve the operation speed.In denoising operation,the fast median filtering algorithm needs to be sorted multiple times,which greatly affects the efficiency of the algorithm.Using the full comparison sorting method,the filtering can process one pixel in 3 clock cycles.This essay introduces FPGA pipeline processing to increase the speed of data processing.For the edge connection in Canny edge detection,multiple iteration loops are required,which is not easy to implement on FPGA.Consider the method of traversing the weak edge image 10 times to determine whether it is an edge point,instead of looping,to reduce resource consumption.2)Propose the parallelization strategy of Hough transform based on FPGA.Considering the problems of the serial Hough transform algorithm with many loops and accumulated arrays occupying numerous memory,propose a parallel optimization method on FPGA.According to the characteristics of Hough transform,design a corresponding parallelization method.Using the parallelization method,the accumulation matrix is divided into multiple sub-matrices for parallel traversal to obtain the local maximum,and then integrate the overall maximum to achieve the result of lane detection.3)Implementation of lane line detection accelerator by FPGA.The development platform chosen in this essay is an ARM+FPGA heterogeneous computing platform,which completes image preprocessing,lane detection,etc.According to the corresponding parallel strategy,this essay first uses OpenCL C language to complete the kernel code writing and implement each module of the accelerator.Then compile it into a.sof file by using Intel OpenCL SDK for FPGA.Finally,download it to DE10 development board for experimental verification,which takes 55.72 ms in total.The code needs to be further optimized to reduce the calculation time.LUT and RAM resources on FPGA are used by 63% and 41%.In the future,optimize algorithms to reduce resource consumption on the basis of ensuring the running speed,so as to achieve the purpose of reducing costs.