The Design Of Lane Line Detection System Based On FPGA

In recent years, with the rapid development of infrastructure and improvement of the national economy, highway mileage and car ownership have rapid growth. At the same time,road accidents also will continue to increase. Therefore, how to decrease the incidence of traffic accidents will become the current hot topic. The research of lane departure warning system is one of the important branches, the system can be an early warning to reduce unintended lane departure behavior of the driver. Given the current market lane detection systems are built on complex algorithms and high-performance hardware platform, resulting related equipment to achieve the high cost, bulky, severely restricted the popularity. Therefore,low cost, miniaturization lane departure warning system is the direction of future research.Among them, the lane line detection is at the heart of LDWS. With the continuous improvement of microelectronics technology, the performance of the chip has also been a huge rise, can meet a variety of large-scale digital system design requirements. At the same time due to the development of EDA technology, but also makes the design based on more flexible, can greatly shorten the development cycle, reduce development effort. These are made to the FPGA core embedded system is extremely suitable for large amounts of lane image data, high-speed, real-time detection.The paper through study the background and significance of the subject, understanding research status, further study related to image pre-processing algorithms and FPGA development technology, completed the design of lane line detection system based on FPGA.System with Altera's Cyclone IV series chip as the core, mainly constitute by the CMOS camera acquisition module, image data storage module, image pre-processing module and image display module. The system using CMOS image sensor to collect real-time image information, and transferred to the SDRAM chip for storage, then carry on a series operation of image pre-processing to storage data, finally obtained the image of lane line detection, to be converted to analog signal output and real-time display on monitor by VGA interface.In the design of the module, mode of the image sensor is configured through the I2C bus to drive the camera for image acquisition. By using incomplete ping-pong operation,asynchronous FIFO operation skills completion of data reads and writes between two different clock frequencies interfaces. Filtering the image information by using a median filter.By use of the image preprocessing algorithm to obtain lane line information. By use of the pipeline, the area of exchange rate and other design ideas to optimization logic circuit, greatly enhances the speed of data transmission and processing.The overall system design based on Quartus ? 13.0 software platform, using software of Matlab 10.0 to complete initial verification of image preprocessing ideas, the eventual adoption of simulation software Modelsim 10.1 simulation verification, to achieve the desired effect by using the core hardware platform self-designed based on EP4CE10E22 chip.Proposed and verify designs in the paper, can provide some reference for the lane departure warning system design.