Research And Design Of Low Noise Low-drop Out Regulator

Under the trend of miniaturization of electronic products,the area of the chip is continuously reduced,the working voltage of the chip is also continuously reduced,and the influence of noise will become more prominent.The power management chip plays a decisive role in the stability and accuracy characteristics of the whole system.As one of the classifications,linear regulators are widely adopted in noise-critical applications due to their simple structure and good noise characteristics.In addition,the Bipolar process has a smaller offset voltage and better noise characteristics than the MOS process.Compared with the MOS process,Bipolar process also has higher driving capability.Therefore,people usually use Bipolar process to design and achieve a good liner regulator.This thesis mainly focuses on the research of related theory and noise characteristics of the linear regulator and designs a low-noise low-dropout linear regulator XD1964.XD1964 is manufactured through 2μm 40 V BJT process.The main research contents of this thesis are summarized as follows:1.The circuit designed in this thesis integrates the amplifier in the traditional voltage reference module with the error amplifier in the loop,making the circuit structure simpler.The noise sources are reduced,which is beneficial to reduce circuit noise.2.The whole loop adopts the Miller compensation method,and the dominant pole of the circuit is located at the output end of the first stage amplifier,and the pole of the output of the LDO is moved to the high frequency position to become the first non-dominant pole.In this way,the capacitance of the output capacitor can be greatly reduced,resulting in higher integration.3.Through the research of the main noise sources and formula derivation,find the main components that affect the noise characteristics,and optimize the parameters of these devices in the circuit design to achieve the purpose of noise reduction.At the same time,an external bypass capacitor port is designed in the circuit,which functions to low-frequency filter the output of the regulator to obtain lower output noise.4.Design over-temperature protection and over-current protection module to prevent thechip from being damaged under abnormal conditions.The over-temperature protection sets a certain amount of hysteresis to prevent the circuit working state from frequently jumping near the over-temperature threshold.5.Complete the circuit layout design.ESD protection processing is designed for each PAD pin to ensure the reliability of the chip.Deep N+ diffusion is used to form the collector of the output transistor,thereby minimizing the collector resistance.The circuit in this thesis realizes a wide input voltage range,the working voltage is-6V~-20 V,the stable output voltage is-5V,and the maximum load current is-200 m A.The Cadence simulation software platform is used to build and simulate the design circuit.Through simulation,the power supply rejection ratio of the circuit reaches 52 d B at low frequency,and the low frequency gain of the whole loop is up to 76 d B.Through the noise reduction method of the external bypass capacitor,the total output noise of the circuit is 22μV in the frequency range of 10 Hz to 100 k Hz.Two layers of metal wiring are used in the layout design process,and the final layout area is 1030 μm×1520 μm.