Design And Application Of FPGA High-speed Transmission Interface In Scope Corders

With the development of scopecorders and other complicated data acquisition systems,the requirements of sampling rate,number of channels,bandwidth,waveform capture rate and storage depth are becoming higher,and the functions of waveform analysis are more and more abundant,however,the transmission rate of waveform data is a critical factor restricting its performance.The development of integrated circuit technology makes FPGA widely used in the field of high-speed transmission,therefore,the study of FPGA high-speed transmission technology is of great significance for improving the performance of scopecorders.This paper focuses on the high-speed transmission of between FPGAs with adaptive bandwidth(2)solution,and the most widely used PCIe high-speed interface is used for the interaction between FPGA and host computer,and focus on the optimal transmission control scheme between data sources with different functions and PCIe bus interface in scopecorder,finally put forward the method of optimizing DMA efficiency.The above two interfaces are applied to the scopecorder,the main content has the following aspects:1.Specific requirements for high-speed transmission are obtained by analyzing the overall scheme requirements of scopecorder.Based on the isolation,high speed,compatibility and other requirements of all kinds of acquisition boards,the most practical transmission scheme between FPGAs is formulated,according to the multifunctional requirements of common acquisition,deep storage,dual capture and real-time operation in the scopecorder,the most suitable scheme for data interaction between FPGA and host computer in this circumstance was selected.2.The serial transmission system between FPGAs with adaptive bandwidth is designed and implemented,including 1.6Gbps high-speed isolation transmission between two slices of FPGA on single channel 100 MSPS high-speed acquisition board,and 3.2Gbps transmission between two slices of FPGA on dual channels acquisition board,and it ensures that phase difference of the two channels in system clock is not generated during the transmission,this system has certain compatibility for high-speed transmission between FPGAs on acquisition boards with different sampling rates and ADC resolutions.3.PCIe high-speed data transmission between FPGA and host computer is designed and implemented,including PCIe hardware circuit design,and the logic design of efficient DMA read/write controller and PIO read/write controller based on PCIe IP core,this part focuses on the transmission control scheme of different memories and PCIe interface,different data sources such as common acquisition FIFO,deep storage DDR3,dual capture SSRAM and real-time operation can be transmitted to the host computer through time-sharing reusing PCIe interface.Finally,the paper analyzes the DMA efficiency of PCIe bus and puts forward some methods to improve it.The test results show that the transmission interface between FPGAs can be adaptive to the bandwidth of 0~4.795 Gbps in single channel,bandwidth utilization is up to 90.82%,the phase difference accuracy between multiple channels after transmission is 10 ns.The DMA controller of PCIe bus supports up to 8MB of data transfer at a time,the PIO controller supports 16 KB of read-write space,the cross-clock transmission control scheme of PCIe interface fully meets the functional requirements of the scopecorder,the DMA transmission rate is doubled in the optimized scheme,but it still has comparatively huge rise space.