Reserarch On Radiation Hardened Technology Of Pipeline And Register File In Processor

With the rapid development of integrated circuits and aerospace technology,the size of devices in integrated circuits has entered the nanometer scale.The improvement of technology has made the transistors contain less and less doped particles,which result in a reduction in the amount of charge carried by the transistors,so the integrated circuit is susceptible to soft errors in the radiation of the spatial particles.The processor is the core control component in aerospace applications,which is mainly used to control the entire system and calculate a large amount of data.If it is not protected,it is susceptible to radiation failure.With the improvement of technology,the density of transistors on the chip increases,and the distance between the memory cells becomes increasingly smaller.The radiation lead to a rise in the probability of multiple bits upsets(MBU)of the memory.The processor has quite high requirements on speed,area and power consumption,so it is of great significance for the research of pipeline and register file radiation hardened design under the condition of low overhead.Based on the OR1200 processor platform,this paper proposes a technique to protect most signals by using the interleaved parity codes combined with the pipeline restart and partial signals by using the Triple Modular Redundancy(TMR)for the pipeline in processor.This paper verifies the function and evaluates the performance of the hardened pipeline.Compared with the unhardened processor,the method of hardening pipeline proposed in this paper can effectively suppress Single Event Upset(SEU),and the critical path delay overhead of pipeline is 7.66%,and the area and power overhead are 16.43% and 14.11%,respectively.This paper proposes a kind of Error Correction Codes(ECC)that can correct random errors in the adjacent 4-bit to harden register file.And based on OR1200 processor,the register file is refreshed by triggering an exception.After comprehensive evaluation,the method of hardening register file proposed in this paper does not affect the critical path delay of the processor,and the area and power overhead are 10.10% and 16.40%.In order to evaluate the harden performance of the register file,this paper proposes a multi-bit fault injection model and implements it.The final results indicates that the hardened register file can correct random errors in the adjacent 4-bit.