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The Design And Implementation For Timing Module Of Airborne High-speed Video Collector

Posted on:2019-02-14Degree:MasterType:Thesis
Country:ChinaCandidate:R YanFull Text:PDF
GTID:2382330572957774Subject:Engineering
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With the development of modern aviation technology,higher and higher requirements have been put forward for airborne video capture.In aviation test tests,the requirements for time accuracy are also increasing.Therefore,based on the needs of aircraft test and test in practical applications,this paper designs and implements the time-based module of high-speed airborne video collector.The main function is to use IRIG_B code timing to realize the demodulation of IRIG_B(DC)and IRIG_B(AC)code and output the standard time in Formation to provide uniform time for equipment in the aircraft test system.IRIG_B(referred to as B code)format time code is an international common time synchronization standard,so the use of B code as a time service method fully complies with the requirements for airborne high-speed video acquisition experiments.Based on the B code,this dissertation firstly completed the hardware circuit design of the time-integrated module of the airborne high-speed video collector,and then used Verilog hardware language to carry out the program design.Finally,the board debugging and system adjustment were performed on the designed board,which verified the implementation of the board function.In the design of the hardware circuit,based on the actual needs and technical indicators,with the aid of Altium Designer software,I completed the circuit schematic design of DC B code demodulation,AC B code demodulation,serial and network port communication and power level conversion.In the process of program design,this paper chose the most widely used and most popular Verilog HDL language in the industry and completed the design of the program through the Quartus II platform.Moreover,in the program design,a modular design idea was adopted to complete the demodulation design of the B code,and finally the demodulation of the B code in the FPGA was realized.The advantage of such a design idea is that it not only can reduce the complexity of the program design,but also provides great convenience for the program in the later design modification,debugging and maintenance.At the end of the paper,a test platform was set up to debug the board that was designed.In order to verify the function of the board,not only did each module in the board be debugged individually,but also the board was placed in the equipment for the system's joint debugging.The test results show that the time-based module of the airborne high-speed video collector completed in this design can output the standard time correctly and the decoding accuracy reaches 1ms,which meets the design requirements of the accuracy.After uniting with the equipment,the board can work normally and provide standard time to the outside.The time-controlled board designed in this paper has the advantages of stable performance,high reliability,strong con Fidentiality,and ease of debugging,and has wide practical application value.
Keywords/Search Tags:high-speed video capture, time synchronization, IRIG_B code, FPGA
PDF Full Text Request
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