| Aiming at the shortage of the types and quantity of optical interfaces of optical transceivers in existing underwater ROV communication systems,this paper proposes and designs this topic: FPGA-based underwater ROV multi-service High Definition video optical transceiver.The entire optical transceiver system is divided into two parts: an underwater transmitting end and a water receiving end,which are connected by an armored opto-electric composite cable.The underwater transmitting end is used to collect video image data and multi-service data such as RS232/485 and Ethernet.After being processed by FPGA time division multiplexing,it is sent to the optical fiber through the SFP+ optical module.The water receiving end is the reverse process,and the received data is demultiplexed by the FPGA to recover the video image data and multi-service data such as RS232/485 and Ethernet.First,the related technical principles used are explained,which highlights the 3G-SDI interface,GTX high-speed serial transceiver technology,and 64B/66 B encoding technology.Among them,GTX high-speed serial transceiver is the focus of this design.The related structure is complex and the setting parameters are many.It is necessary to understand the operating principle.In addition,two schemes were designed according to the existing technology,and the scheme of the built-in FPGA transceiver was selected through comparative analysis.Secondly,the hardware circuit of each module is designed and analyzed,including FPGA circuit,3G-SDI circuit,analog video circuit,RS232/485 circuit,Ethernet circuit,clock circuit,SFP+ optical module circuit,DDR3 circuit and power supply circuit.It also introduces the PCB design process in detail,explains the PCB stack structure and impedance control method,and describes the DDR3 trace topology and the PCB medium long constraint design.Thirdly,it focuses on the process of FPGA logic code implementation,especially the encapsulation and decapsulation process when the FPGA uses the on-chip high-speed transceiver to send and receive data.The data encapsulation at the transmitting end is to package the collected video image data and multi-service data such as RS232/485 and Ethernet into 64-bit parallel data,which is then sent by the GTX transceiver.The data decapsulation at the receiving end is to unpack the 64-bit parallel data received by the GTX transceiver,and recover the original video image data and multi-service data such as RS232/485 and Ethernet.Two important IP cores in FPGA logic design are also detailed: Aurora 64B/66 B and SMPTE SD/HD/3G-SDI.Finally,this paper describes the debugging process of each module of the system,including hardware test,3G-SDI transmit module test,3G-SDI receive module test,high-speed serial link test.After the test of each module is normal,the system is coordinated,realizing the real-time transmission of 2 3G-SDI signals,4 analog videos,16 RS232/485 data and 1 Gigabit Ethernet data. |
