Asynchronous Readout Circuit With Priority Arbitration For SPAD Arrays

Single photon avalanche diode array detectors with high sensitivity,strong integration,fast detection speed,low power consumption,and ability to detect extremely weak optical signals are widely used in biological research,fluorescence lifetime measurement,laser imaging radar and other aspects.The photon detection information on each pixel needs to be accurately recorded and output by the readout circuit designed with the SPAD detector array in different applications.So the readout circuit is very important to the performance of the detectors.In recent years,research on SPAD imaging technology at home and abroad is rapidly developing,but China is still at the entry-level in research,design and application of large-scale SPAD arrays and readout circuits.After research,the clock-driven synchronous readout circuit is still used by most applications,and there is a large amount of redundant data,which causes the transmission bandwidth to be severely limited.In order to overcome this speed limitation,an optimized multi-channel parallel readout circuit has been proposed to increase the relative speed through TDC channel sharing.However,due to the limited number of shared TDC channels,readout conflicts of effective photons cannot be alleviated,and there is a waste of shared resources under the weak light conditions of uneven lighting.To solve the problem of redundant data and read conflicts,a new full-parallel array asynchronous readout method is designed for the application characteristics of SPAD,which allows photon detection and readout of different pixels to be synchronized.The measured time value of the hit pixel in the array and the corresponding two-dimensional coordinate address value can be read out and stored in real time.In this thesis,first,a modeling method of random signal source is proposed for the randomness of the photon in time and position distribution,and the distribution is verified by SPSS software.Secondly,for the core asynchronous readout,on the one hand,a new pixel structure and system architecture have been established.Priority arbitration for the readout order of pixels is completed by combing flip-flops and counters which are used to distinguish hit and readout states of pixels with external comparison logic.On the other hand,the structure of each module of the proposed readout circuit is designed and analyzed in detail,and the function simulation and timing simulation of each module are performed by FPGA.Finally,the readout data is uploaded to the PC for display via the UART serial bus,which verifies the accuracy and feasibility of the proposed readout circuit,and lays the foundation for larger-scale array research.The experimental results show that the readout speed of the proposed asynchronous readout circuit in this thesis is better than the synchronous readout circuit.Because only the information of hit pixels are read out,that is,the redundant data is eliminated from the source.At the same time,due to the full parallel arbitration of the pixel array,the accumulation effect in the traditional shared asynchronous readout circuits is avoided.