Study Of Detection System Of Single Event Upset Based On FPGA

Field Programmable Gate Array(FPGA)is widely used in many current space electronic systems due to its short design cycle,reprogrammable,low cost,and flexible operation.However,as integrated circuits enter the nanoscale,the risk of single-event upset(SEU)in FPGAs is increased by space radiation,which in turn affects the effectiveness of the information stored in the internal memory cells of the FPGA,causing electronic system failure.Therefore,the research on the detection of the SEU effect in FPGA has important practical value.Based on the FPGA development board,this paper studies and implements a SEU detection system,which can be used to detect and evaluate the SEU effect of the trigger unit in the FPGA circuit.The detection system consists of four parts: a test vector generation module,a test result analysis module,a synchronization control module,and a test result uploading module.The test vector generation module can provide a test vector for the FPGA circuit to be tested inserted into the scan chain;the test result analysis module receives the response from the FPGA unit to be tested,and performs logic judgment within the FPGA detection system to determine whether the test response is expected or not.The same,to determine whether the SEU effect occurs in the FPGA to be tested,and count the number of failed flip-flops;the synchronous control module is used to implement the protocol handshake between the FPGA detection system,the FPGA circuit to be tested,and the SEU fault injection device.The test result uploading module is used to count the number of triggers that generate SEU,and uploads the number of failed triggers to the host computer through the serial port RS232.Through the joint action of the above four modules,the detection of the SEU effect in the FPGA circuit to be tested is realized.Using the SEU detection system developed in this paper,the detection and evaluation of the SEU effect in the ISCAS'89 reference circuit based on FPGA after heavy ion irradiation experiment is emphasized.The experimental results show that the developed detection system can accurately detect the circuit under test.Whether the SEU effect occurs in the trigger unit,and the number of triggers in which SEU occurs can be counted,which is completely applicable to the actual detection requirement of the SEU effect in the target FPGA circuit.