Design And Implementation Of Low Noise Chopper-Stabilized Analog Front-End For Bio-Potential Acquisition

Since the establishment of the biopotential theory,biopotential signals have become an important means of medical monitoring and diagnosis.With the aging of the population,the traditional biopotential signal acquisition system cannot meet the demands of the real-time portable monitoring in the daily life.Therefore,the portable acquisition equipment has become the trend of the medical monitoring system.As the interface circuit between the acquisition electrode and the subsequent circuit in a portable device,the performance of the analog front-end determines the quality of the signal acquisition.Therefore,biopotential acquisition front-end needs to deal with many challenges,such as low noise,low power consumption,high input impedance,and high common-mode rejection ratio.This thesis is to design an acquisition chip for a variety of biopotential signals.First of all,literature surveys have been done on the design of the biopotential acquisition analog front-end,and the architecture of the system and the design parameters are discussed and determined considering the characteristics of the biopotentials.After that the design of every sub-module of the open-loop chopper-stabilized amplifier is introduced,including chopper modulator,pseudo resistor,operational transconductance amplifier and the impedance boosting loop.Compared with the existing research,the innovations of this thesis are shown as follows:firstly,the amplifier adopts the global open-loop chopping modulation,which effectively suppresses the overall noise of the amplifier and the device mismatch.Secondly,the pseudo floating gate structure is utilized in the transconductance amplifier to achieve the operation mode of push-pull in the output stage,which can increase driving capability of the circuit.Thirdly,the impedance boosting loop is employed in the amplifier to suppress the impact of chopping modulation on the input impedance and improve signal acquisition quality.The chip is designed and fabricated under the XFAB 0.35?m CMOS process.According to the post-layout simulation results,the analog front-end achieves power consumption of 7.84?A from a 3 V supply and the input referred noise of 0.67?V_rms for a bandwidth of 0.5-150 Hz.Then the input impedance reaches 15.7 M?at 20 Hz.The front-end also achieves 46-64 dB tunable gain with the high-cutoff frequency lower than 0.2 Hz and the low-cutoff frequency of 60-200 Hz.The common mode rejection ratio reaches131 dB at 50 Hz,and the power supply rejection ratio achieves 104 dB at 50Hz.What's more,the noise efficiency factor of the front-end is 8.9.So the chip achieves good performances under low power consumption.