Research On Key Techniques Of Analog Front End For ECG Acquisition

In recent years,with the increasing aging of the global population,as well as people's increasing attention to their own health,the wearable biomedical equipment is receiving more and more attention,and its market value and application prospects are becoming broader.As the key module of the wearable device,the analog front end(AFE)achieves the amplification,filtering and digitization of the weak bioelectric signals.Its performance determines the accuracy of the acquired bioelectric signals.The amplitudes of the bioelectric signals are generally distributed in the order of microvolts to millivolts,and their frequencies are between several hertz to several hundred hertz,which leads that the bioelectric signals are extremely easily submerged in the low-frequency noise of the circuit.At the same time,the influence of electrode DC offset(EDO),power frequency interference,motion artifacts and other factors also brings many challenges for bioelectric signals acquisition.Therefore,it is one of the mainstream research directions of the contemporary biomedical electronics industry to study the key design techniques and realize the high-performance of the AFE with low noise,low power consumption,strong anti-interference ability,and small chip area.This thesis studies the key technology of analog front end for elctrocardiogram(ECG)acquisition.First,the characteristics of ECG are analyzed;Second,the noise and interference sources in the ECG acquisition AFE are summarized,the method of eliminating interference in the ECG acquisition AFE is studied,and performance indicators that the ECG acquisition AFE needs to meet are given,also,the circuit architecture of the ECG acquisition is analyzed,the key design techniques for reducing power consumption and noise in the ECG acquisition AFE are researched;Finally,the structure and design scheme of the low-noise,low-voltage and low-power ECG acquisition AFE are determined.Based on the above research,this thesis designed and implemented a low-noise,low-power ECG acquisition AFE chip.It integrated a low-noise capacitively coupled chopper instrumentation amplifier(CCIA),a programmable gain amplifier(PGA),a GM-C low-pass filter(GM-C LPF),and a successive approximation analog to digital converter(SAR ADC).The chopper modulation technique is employed in the instrumentation amplifier to reduce the low frequency noise of the AFE.Meanwhile,a novel chopper-capacitor-chopper integrator based DC servo loop(C³IB-DSL)with low noise,low PVT sensitivity is proposed to suppress the EDO.A PGA followed by the CCIA is applied to realize the configurable gain of the AFE to meet the dynamic range of the SAR ADC.A GM-C LPF is utilized to filter out high-frequency noise,spikes and interference signals.The input MOS pair of the GM cell is biased in the sub-threshold region for low power and small chip area of the GM-C LPF.Besides,an inverse hyperbolic tangent pre-distortion circuit is proposed to extend the linear input range of the GM cell,improving the linearity of GM-C LPF.The chip was designed and fabricated in SMIC 0.18?m CMOS process.The measurement results show that the overall power consumption of the AFE is 3.5?W;The input referred noise spectral density of the CCIA is 74n V/?Hz,while its integrated noise in the bandwidth of 0.5-100Hz is 1.16?V_rms;The EDO cancellation range of AFE is±90 m V and the effective number of the SAR ADC is 9.06bit.The proposed AFE has been experimented with capturing the ECG of the human body successfully.This thesis also designed a low-noise,high precision ECG acquisition AFE with dual power supply mode to further optimize its performance.The AFE includes a CCIA,a GM-C LPF and a continuous time sigma-delta modulator(CT?-?M).The power consumption and EDO cancellation range of the AFE are optimized via the combination of the high level and low level power supply,while employs a common-mode feedforward circuit in the CCIA to suppress the common mode voltage drift of the AFE.Finally,the AFE circuit is designed and verified by simulation based on TSMC 65 nm CMOS process.The simulation results show that the input referred integrated noise of CCIA is 0.73?V_rms from the bandwidth of0.6-100Hz,the overall power consumption of the CCIA and GM-C LPF is 5?W,and the effective number of the CT?-?modulator is 12.66bit,while the EDO cancellation range of the AFE is±200m V.