Design Of Dynamic Error Extraction Circuit Based On Dynamic-Mismatch Mapping Correction Algorithm

In the 21st century,with the rapid development of microelectronic technology and communication technology,the speed of Signal processing and transmission is getting faster in the chip.Current-steering DAC(Digital to analog converter)architecture is widely used in communications because of its advantages of high resolution,high speed,and easy operation.High-precision and high-speed current-steering DAC have increasingly become one of the hotspots of current research.The dynamic performance of current-steering DAC will be obviously decreased because of timing error instead of static error.Mainstream correction algorithms,such as self-calibration techniques and switching-sequence post-adjustment calibration technology,are used to correct the static error of the current source,and there is no improvement in the dynamic performance of the DAC at high frequencies.However,the Dynamic-Mismatch Mapping(DMM)correction algorithm focuses on reducing the dynamic error of the current source,which can significantly improve the dynamic performance of the current-steering DAC at high frequencies.Because the precision of the dynamic error extraction circuit will directly determine the performance of the DMM correction algorithm,in order to take full advantage of the advanced technology and improve the performance of DMM correction algorithm,this paper will design a high-precision low-power dynamic error extraction circuit based on the standard 40nm CMOS process.The dynamic error extraction circuit includes a low-noise current-driven double-balanced passive mixer circuit and a low-noise low-power transimpedance filter circuit.This paper optimizes the dimension parameters of the mixer and designs a special buffer circuit of local oscillator signal,which greatly reduce the noise of the mixer and the effect of mixer on the noise of transimpedance filter circuit.In addition,this paper can ensure that the dynamic error extraction circuit can extract accurate I/Q data.Based on the considerations of noise,gain and power consumption,the paper combines nested chopping technology and gain bootstrap technology into the design of fully differential amp.Then because of the particularity of the fully differential operational amplifier architecture,the paper designed a special common mode feedback circuit,which significantly reduces the power consumption of the amplifier.Finally,with the technology of low-power design and high-order curvature compensation,this paper proposes a new type of high-precision resistor-free reference circuit architecture in order to reduce the power consumption of the overall reference circuit and the temperature coefficient of the output reference voltage effectively.Based on the standard 40nm CMOS process,this paper completes the circuit design and simulates the mixer circuit and the transimpedance filter circuit separately.Simulation results show that the noise figure of the mixer circuit is 3.467dB,the overall gain of the transimpedance filter is 92dB,and its bandwidth is 2MHz.Then the paper complete the overall layout design of the dynamic error extraction circuit,the parasitic parameters of this circuit are extracted and the circuit is simulated for the overall performance verification,and the area of layout is 0.125mm~2.The precision of the dynamic error extraction circuit is 5nA amplitude error and 0.4ps timing error,P1dB is equal to 0.449mA,and IIP3 is equal to 0.942mA,and the equivalent output noise integrated voltage is 17.176?V(integral range is 10Hz~1MHz).The consumption is7.25mW,and the overall performance meets the design requirements.