Research And Implementation Of Multi-User Downlink Data Sharing Channel Baesd On TDD-LTE Technology

The amount of data in communications has increased significantly in a virtual and realistic world environment.Higher requirements for the performance of wireless communication hardware platforms have been required,and TI introduces multi-core digital signal processor TMS320C6670 based on KeyStone I architecture supporting multiple wireless protocols.The thesis studies the implementation of the Physical Downlink Shared Channel(PDSCH)based on the hardware platform,completes the joint adjustment of the scheduling layer,the physical layer and RF board under a variety of typical bandwidth configuration conditions and different number of users,and finally,the transmission performance of PDSCH is tested and verified under typical fading channel conditions.The thesis first studied the TDD-LTE physical layer protocol,the overall flow of the base station side and user equipment side of PDSCH using single antenna,transmit diversity,and space division multiplex transmission mode under 5MHz,10 MHz,and 20 MHz bandwidths is designed and divided into multiple sub-modules.The thesis analyzes the key sub-module algorithm selection and process in detail.The floating-point link simulation platform is set up using Matlab.The correctness of the simulation link of PDSCH in Gaussian channel and Rayleigh channel under different bandwidths and different transmission modes is verified.The floating-point link provides performance reference for fixed-point link implementation based on Digital Signal Processor(DSP).The thesis focuses on the DSP software implementation of the PDSCH,and analyzes overall design and multi-core processing of software modules at the base station side and user equipment side based on analysis of computing resources of multi-core data processing chips.The thesis completes the configuration and implementation of Fast Fourier Transform Coprocessor(FFTC)and Bit Coprocessor(BCP)carried by TMS320C6670,and testes and optimizes the coprocessores.The thesis studies the allocation of DSP storage space and analyzes the caching mechanism in detail.It provides a reference for the software implementation of data sharing between multiple cores.The thesis completes the DSP software implementation of the base station side link such as Turbo channel coding,layer mapping,precoding,and OFDM symbol generation,and completes the DSP software implementation of the user equipment side such as resource demapping,channel estimation,channel equalization,soft demodulation,and channel decoding.The thesis completed the joint test of the prototype,and designes the data interaction scheme of the physical layer and the scheduling layer implemented in the following two ways the serial port and the network interface.The advantages and disadvantages of the two methods are compared.The data exchange program of the DSP and FPGA interface is designed.Link system-level joint testing verifies the correctness and stability of the interface scheme;the thesis designs the calibration scheme for fixed-point implementation and compares it with floating-point link for verification and optimization.The thesis completes the demonstration system construction based on computer,multi-core chip,RF board,and antenna.The thesis realizes the data transmission service between base station side and user equipment side based on TDD-LTE technology,and initially fulfills the project requirements.Finally,the thesis summarizes the research results of the whole paper,and proposes further research directions for the PDSCH.