Research On The Key Technologies And The Implementation Of The Multi-User Pdsch Of TD-LTE System

The rapid development of the wireless technology leads to the higher requirement of the performance of the hardware platform.To support different wireless standards, TI provided multi-core DSP TMS320C6670 based on the KeyStone I architecture. TMS320C6670 has four DSP cores with frequency of up to 1.2GHz and integrates different hardware accelerators to reduce the requirment of DSP processing.This thesis mainly studies the implementation of TD-LTE downlink physical channel based on TMS320C6670.This thesis studies Physical Downlink Shared Channel(PDSCH) and Physical Broadcast Channel(PBCH) of TD-LTE, analyses the transmission processing of PDSCH and PBCH, extracts the sub-module and chooses the algorithm of the key module.This thesis builds the float simulation link with Matlab and compares the export data with the standard result to verify the processing of the send link.The simulation result is given to verify the feasibility of the algorithm and provide the performance reference for the implemention of DSP.This thesis deeply studies the implemenion technology of multi-user PDSCH and PBCH based on TMS320C6670 DSP.This thesis studies the send processing of downlink multi-user data,including the bit processing with Bit Coprocessor(BCP), multi-antenna processing and port mapping processing,the ifft processing with Fast Fourier Transformation Coprocessor(FFTC).This thesis analyses and designs the pipeline processing with four DSP cores to implement the PDSCH receiver under peak rate, including the symbol fft based on FFTC, the prb demapping,the channel estimation based on least squares algorithm and linear interpolation algorithm,the channel equalization based on least squares algorithm,soft demodulation,descramble,the deratemating based on BCP and turbo decoding and crc checking based on Turbo-Decoder Coprocessor(TCP3D).This thesis studies the PBCH receive processing.The receiver may have to process up to four times to get the MIB,this thesis analyses the receiver processing and the complexity, and finish the implemention with DSP.This thesis analyses and verifies the feasibility of the resource allocation of DSP, verfies the correctness of the link through comparing the DSP module with Matlab module. This thesis compares the bit error rate with float simulation result and verfies the performance of the link.This thesis designs the system testing scheme and finish the test combined with FPGA and RF board, verifying the performance and stability of the system through the channel simulator.