Research And Implementation Of The Physical Downlink Shared Channel For Broadband Wireless Multimedia Trunking

This thesis studies the key technology of implementing the Physical Downlink Shared Channel(PDSCH)of broadband wireless multimedia cluster based on TD-LTE.Based on TI's TMS320C6670 quad-core DSP chip,the DSP software of the transceiver link is completed.The interface between the PHY and the MAC layer is designed,and the data interface between the DSP and the FPGA is designed.The accuracy and stability of the system are verified by the system cascade test.The performance of the test prototype in the typical channel is verified by the channel simulator.This thesis first studies the TD-LTE physical layer protocol,designs the overall flow of the downlink data sharing channel based on the protocol,and analyzes the algorithm selection and processing flow of the key sub-module in detail.Based on Matlab software,the link-level floating point simulation platform of sender and receiver is set up.By comparing the data with the third-party standard link,the correctness of the link is verified and the performance of the simulation link is verified under the Gaussian channel.This thesis focuses on the realization of DSP software for downlink data sharing channel.Based on the resource analysis,the overall design and multi-kernel partitioning of the function module of the transceiver software are studied.The mechanism of multi-core data navigation of TMS320C6670 chip is studied,and the fast Fourier transform coprocessor,Bit-coprocessor,and the performance of coprocessor is tested and optimized.The paper completes the DSP software of sending link bit-level sub-module and symbol-level sub-module.DSP software implementation of sub-modules such as link resource allocation,channel estimation,channel equalization,soft demodulation,solution rate matching,channel decoding and CRC check.The thesis first completed the DSP self-loop test.Based on the test requirements,the basic principle of the TMS320C6670 interrupt is studied.Based on the timer interrupt and the Doorbell doorbell interrupt in the SRIO interface,the interface scheme of the DSP self-loop test mode of the downlink data sharing channel is completed and the system is processed continuously.Capability and stability of the DSP.The paper compares the main modules of the DSP fixed-point implementation with the Matlab simulation link,and verifies the correctness of the link.The complexity of the link and the receiving link and the storage of the resource Conducted a test analysis.The paper has completed the joint test of the test prototype.In this paper,the data interaction scheme between PHY layer and MAC layer interface is designed,and the data interaction scheme between DSP and FPGA interface is designed.The correctness and stability of the interface are verified by the downlink system cascade test.Based on the channel equalization module,Data calibration is carried out,and a calibration scheme based on dynamic calibration is proposed.The performance of the system is tested by the performance test scheme of the channel simulator.Finally,the paper summarizes the research results of the whole paper and puts forward the direction of the next research.