Font Size: a A A

The Study Of Low Power Digital-domain CMOS-TDI Image Sensor Readout Circuit

Posted on:2018-07-23Degree:MasterType:Thesis
Country:ChinaCandidate:C W YuFull Text:PDF
GTID:2348330542979460Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The CMOS time delay integration?TDI?image sensor adopts more rows of pixels to scan the same object,and the integrated signal are accumulated together.Thus,a better signal to noise ratio?SNR?can be achieved using a TDI image sensor.Digital-domain accumulation scheme is a very practical implementation scheme of CMOS-TDI image sensor.The analog-to-digital converter?ADC?of digital-domain CMOS-TDI image sensor will implement the full process of quantization for an accumulation.Therefore,at high speed scanning and high accumulation stages,large amount of data generated by ADC may bring in more power consumption.The paper studies the low power readout circuit of digital-domain CMOS-TDI image sensor.Firstly,the paper analyses the working principle of the traditional digital-domain TDI accumulation scheme.The paper propose the low power digital-domian accumulation scheme based on the accumulation characteristics of the digital-domain TDI accumulation scheme.The pixel array is divided into two groups:one is for coarse quantization of high bits only,and the other one is for fine quantization of low bits.Then,the complete quantization codes are composed of both results from the coarse-and-fine quantization.The optimized implementation scheme is discussed,and a behavioral simulation is completed with MATLAB.In order to vertify the proposed accumulation scheme,two versions of 16-stage digital-domain CMOS TDI image sensor chains,with and without the proposed technique,are designed.The image sensor chain mainly consists of pixel circuit,digital programmable gain amplifier,successive approximate register?SAR?ADC and digital-domain accumulator.In the 0.18?m CMOS process,two versions of 16-stage digital domain CMOS TDI image sensor chains are designed.The post-simulation precision of SAR ADC is9.59-bit with an input frequency 400kHz at a 1.96MS/s sampling rate.The simulation results show that the linearity of the two versions are 99.74%with the proposed accumulation scheme and 99.99%with the traditional accumulation scheme,respectively.Meanwhile,the average power consumption of slices of the two versions are 6.47×10-8J/line 7.4×10-8J/line,respectively.
Keywords/Search Tags:low power, digital-domain CMOS-TDI image sensor, coarse quantization, fine quantization
PDF Full Text Request
Related items