Design And Implementation Of Programmable Digital Filter For SDR

With the rapid development of information age,digital signal processing has become an important subject and technology.The digital signal processing module is the core module of SDR(Software Define Radio),which expects the digital signal processing module to process the digital signal after ADC in real time and adopt the software method to complete the wireless function.Digital filter is one of the key functional blocks in digital signal processing.In practice,the rate of zero-intermediate frequency signal after AD conversion is usually very high,which requires high design of the circuit.In order to satisfy the requirements of multi-rate digital signal processing,the designed digital filter must realize programmable functions based on data domain filtering and decimation,the demand of frequency bands in various communication modes.Therefore,the design and implementation of programmable digital filter is of great significance.In this paper,ARM + FPGA architecture was designed to achieve a programmable digital filter between the SDR zero intermediate frequency signal and baseband signal.The paper mainly completed the following work: Firstly,the FIR filter design parameters and simulation environment are determined,among which design indicators include variable order(Maximum Number of Taps is 128 steps),adjustable gain and variable decimation or interpolation factors.Secondly,according to the design requirements of this paper,the simulation circuit is built in Simulink environment of MATLAB.The filtering effect of digital filter with different modes and different filtering environments is verified,and the simulation results and design indexes are compared at any time,optimizing the design of the filter quickly and conveniently,and then the digital filter structure adapting to the actual engineering is determined.Finally,the programmable digital filter is achieved by using xilinx zynq series FPGA device,verilog_HDL RTL language is used to complete the circuit design,and circuit RTL level simulation is conducted in NC_verilog or ISE integrated software environment,Through MATLAB software to help FPGA design of the digital filter simulation verification.The simulation results show that the programmable digital filter designed in this paper is correct and the occupied resources are relatively small,Additionally,the filtered signal spectrum meets the design requirements.The FPGA is embedded in the ARMCortex-A9MPCore processor core,which can realize filter group function configuration via the software configuration,greatly improving the filter design efficiency.