BWDSP100-based Radar Echo Real-time Transmission And Processing Program Design

With the rapid development of microelectronics technologies,radar system is advancing in the direction of digital,intelligent and mega data.The radar system signal processor should have the capability of high speed data transmission,massive data throughput and high efficiency in data processing,however,conventional signal processors have difficulty in completing the functions above.Signal processing platform which composed by FPGA and DSP has powerful computing capability,supports flexible reconstruction of system solutions,and has been widely used in various high-speed data processing field.In this paper,the hardware platform of program design is based on the FPGA+DSP architecture which consists of four DSPs of BWDSP100 and one high-performance FPGA.Thereinto,BWDSP100 is a self-developed high-performance digital signal processor.The manufacturing process of BWDSP100 is based on 55 nm technologies,which ensure a large scale composition.The DSP adopts four cores parallel processing structure,and has a powerful float-point calculation ability,which meets the requirements of high-speed and real-time signal processing.The main study of this thesis is to accomplish the program design for real-time transmission and processing of radar echoes in a radar experiment system,including real-time transmission logic module design by FPGA and real-time data processing by DSP.Firstly,in according with the hardware resources of the radar system,an optical fiber is used for data exchange between the timing control board and the signal processing board,the structure of optical module and the configuration of the IP cores is also introduced in this paper.According to the coupling pattern of Link connection between DSP and FPGA of the signal processing board,the paper assignes the signal processing task for FPGA and DSP.FPGA exchanges data between the signal processing board and the timing control board,and realizes the Link transmission module in strict compliance with the Link protocol and timing constraints premise,by optimizing the programming and control codes,the Link module is achieved to be controlled and recycled.Since the frame data output of the timing control board is real-time uncontrollable,FPGA adopts a ping-pong RAM structure to receive the real-time data,and uses a dual-link module to solve the problem caused by the inconsistence between the writing and reading rate of the ping-pong RAM in the data receving path.Using a cooperative control module to meet the strict timing requirements between diffierent modules;Secondly,according to the Link connection pattern of the four BWDSP100 s on the signal processing board,the four DSPs are divided into two main control pieces and two ping-pong process sheet.The work timing and processing program of DSP is also designed in this paper.By simulating the real-time processing situation,the design of the program is verified to be rationality and feasibility.An example is presented to demonstrate the method of using the four Macros of DSP to achieve the parallel program design.Finally,partial results of system joint debugging are given,the results show that the design of the software basically meet the requirements of real-time transmission and processing for radar echoes,and this layes the foundation for future software development.