Research On And Hardware Realization Of The Acquisition And Tracking Algorithm Of BDS-1I Satellite Signals

With the continuous development and improvement of BDS in recent years,BDS is playing a more and more important role in civil and military applications.As the key technology in the navigation receiver,the acquisition and tracking algorithm has become the hotspot of research.This thesis researches on BDS-1I signal,and designs and verifies a BDS-1I signal acquisition and tracking circuit by FPGA,and finally demodulates the satellite ephemeris.Based on this design,a low-cost and low-power BDS acquisition tracking chip is implemented that provides basic parameters for satellite navigation and positioning calculations.This thesis firstly introduces the BDS-1I signals and the architecture of BDS receiver,and then analyzes and compares the serial correlation algorithm and parallel correlation algorithm for the satellite acquisition tracking;the BDS-1I signal acquisition circuit is designed by using of the time-domain serial acquisition algorithm which costs less hardware resource,the multi-path parallel correlation algorithm to improve acquisition speed and the real pseudo identification algorithm to reduce false alarm probability to effectively obtain the visual satellite number,C/A code phase and Doppler frequencies;the tracking circuit is designed to eliminate the effect of the secondary coding and capable of tracing both the C/A code phase and the Doppler frequency,which uses the ordinary E/P/L comparison algorithm to trace the C/A code phase and the frequency scanning algorithm to trace the Doppler frequency;based on the correct tracking,the satellite ephemeris is demodulated by means of the sub-frame preamble recognition and BCH error correction;the demodulated ephemeris is uploaded into computer by UART and some of the basic parameters such as the preamble code of BDS,ID of the sub-frames,SOW(second of week)etc.,are extracted to basically verify the correctness of the proposed circuit.This thesis also uses SMIC 0.18 um CMOS process to implements the verified Verilog code into ASIC through the standard digital integrated circuit design process,which includes logic synthesis based on DFT,static timing analysis(STA),formal verification,automatic test pattern generation(ATPG),place and route(P&R),DRC,LVS,as well as metal dummy additions.This thesis researches on the BDS-1I signal acquisition tracking algorithm,designs and realizes the algorithm by Verilog coding and FPGA verification,and implements the Verilog code into GDSII.The proposed work in this thesis is helpful to a BDS receiver design.