Design Of Blind Equalizer In 64QAM System

Blind equalizer,as a key technology in high speed digital communication system,can restore the original signal only according to the statistic identity of signals without sending training sequences.But in multipath fading channel,the high-order QAM signal is more sensitive to channel distortion,and the single mode Bussgang blind equalizer has balanced the contradiction between speed and accuracy.Hence,the research in the dual mode Bussgang blind equalizer of faster convergence speed and less steady state error is of great significance.This paper has carried on analysis of the limitation on CMA DD dual mode Bussgang blind equalizer in high order QAM system and then has made further improvement.In the capture mode,firstly introduce multimode ideas in the cost function of CMA algorithm to optimize the phase shift and improve the effect of equilibrium,then further explore the effect of the step length on the convergence rate and introduce a proper weight coefficient to realize stable and rapid capture of the intersymbol interference(ISI)in channel;when the eye diagram of the channel has opened,then smoothly switch to the tracking mode,introduce the idea of respectively consider the real and virtual part of signals in the decision guide DD LMS algorithm with weighted optimization,so as to adapt to multidimensional signals and then achieve less steady residual error.This paper has further solved the hardware design of the blind equalize on the FPGA platform.The hardware measurement of the improved blind equalizer for high-order QAM system is mainly from two aspects of function and performance.Test results show that its hardware resources increases slightly,but it can keep the bit error rate(BER)below 10-4 and the remaining steady-state error(MSE)below 10-2 under an input-SNR of 30dB,better than the existing algorithm.The blind equalizer designed for high-order QAM system in this paper has achieved the desired design index.It also shows good work performance.The research results have a certain practical significance for the current channel equalization of the high speed digital communication system.