The Realization Of H.264 Codec Based On FPGA

H.264 video compression standard is the most popular and mature video compression standard in recent years,foreign researchers on the H.264 hardware codec IP core implementation has done a very high level.In view of the use of such IP core can't meet the specific parameters of the various scenarios through the relevant parameters and the use of such IP core need to pay expensive costs,so our own development of H.264 video codec hardware system is very necessary and challenging.H.264 video compression standard excellent compression performance is high complexity and large computational cost to achieve the cost,in order to make this H.264 intra-frame video codec system hardware development cycle is relatively short,the design complexity is relatively lower,and design work is relatively lower.Based on the Xilinx HLS development tool,this paper proposes an embedded architecture of H.264 intra-frame video compression coding system,and realizes the hardware development of H.264 intra-frame video codec system in the higher level.In this paper,we adopt the Micro Blaze embedded soft-core implementation for the rate control module in the embedded architecture,and optimize the algorithm of the rate control module so that the rate control of the first frame coded image can be completed in 600 us,the rate control of the others coded image can be completed within 13 us,which means that the speed of rate control does not affect the speed of the whole intra-coding system.In this paper,we adopt a line of one macroblock storage logic for the macroblock reference information loading and updating module in the embedded architecture,which reduces the storage logic of storing all the macroblock reference information of one frame of the encoded image 26% of the BRAM use,to avoid the waste of hardware resources.In this paper,Intra4×4,Intra16×16 and Intra8×8 are proposed in parallel and each of them prediction mode is implemented in parallel with the intra prediction and reconstruction module in the embedded architecture.The prediction formula of the nine prediction modes of Intra4×4 prediction mode is put forward,the reconstruction is carried out so that the calculation of the nine prediction modes can be completed in one clock cycle and further take the 4? 4 sub-block 16 pixels in parallel,the non-reference pixel is not reconstructed and only the effective prediction mode is selected to compare the method to speed up theIntra4×4 prediction mode achieve;at the same time,16×16 blocks are divided into 16 4×4 subblocks according to the increment law between 4×4 subblocks and 4×4 subblocks in the plane prediction mode of Intra16×16 and Intra8×8 prediction mode,further,only the reconstruction of the reference pixel is realized in Intra16×16 prediction mode implementation,and reduce the Intra16×16 prediction mode of resource consumption.In this paper,the HLS simulation results of the embedded architecture are consistent with the hardware implementation results,that is,the coding speed is 1.68 cycles / pixel,enough to deal with 1080 P @ 25 Hz video sequence real-time coding.In this paper,the subjective evaluation and objective evaluation of the image quality before the embedded architecture compression coding and after the hardware decoding are used to further demonstrate the effectiveness and feasibility of the embedded architecture to realize the H.264 intra-coding system.