Design And Implementation Of Read&Write DMA Engine Based On RapidIO

In embedded multicore interconnected systems,how to define the communication of chips has become a problem which cannot be ignored,thus establishing a common multicore interconnected protocol standard is very necessary.Rapid IO(Rapid Input Output)high-speed serial interface can completely meet this requirement,it can be implemented on-chip and out-chip communication network,and supports a variety of topologies.Rapid IO supports a variety of transmission modes,PIO(Program IO)is the most common mode of transmission mode.Because it needs to use EDMA(Enhanced Direct Memory Access)component and address mapping,therefore the system will result in waste of resources and increase the complexity of the transmission when achieving high-volume data transmission.To reducing the loss of performance,designing the read&write DMA engine which is based on an commercial DMA(Direct Memory Access)IP Core controller and the characteristic of Rapid IO,main work is as follows:(1)Studying the composition of Rapid IO 2.1 protocol,describing the component of logic layer in detail,analyzing the APIO(AXI-PIO)operation and the RPIO(Rapid IO-PIO)operation,and address mapping are discussed,it fetches the PIO transmission mode and DMA transmission mode.(2)Designing two completely independent read/write DMA engine according to the Rapid IO architecture and protocol.Showing two ways that the configuration can be achieved,taking into account the size inconsistencies of a transfer between AXI requests and RIO(Rapid IO)request,and instituting the rule of segment based on AXI protocol and the width of data buffers;researching the way of data endian conversion and determining the order of data outflowing the DMA engine,designing the overall block diagram of read&write DMA engine.(3)Designing the function unit of read&write DMA engine,including the packet format processing unit.Determining the rule of more detailed divided request and the way of data representation size.Describing the specific steps of design from IB(Inbound)and OB(Outbound)direction.Studying the special case of a word transmission and non-aligned address transmission primarily,and giving the solutions.Investigating the reason of design in this way according to compare the read&write engine.(4)Verifying read&write DMA engine design in system-level simulation,while adding to the core code RC synthesis,the lowest clock frequency is 333Mhz;testing the RIO data path in different storage spaces.Results show that the design of DMA engine achieves the bandwidth of 6.25 Gbps.Accomplishing the same task with PIO transmission mode and DMA transmission mode,comparing in four areas.The results show that when transferring large amounts of data using DMA mode,the reduction of configuration register number is 29%,the reduction of start delay is up to 20.5%,the reduction of transmission time-consuming is about 0.6%,the reduction of power consumption is more than one times.