The Design Of 10bit Ultra Low Power SAR ADC

Successive approximation(SAR)ADC has been widely used in the low power consumption field such as sensor networks and biological chips,due to its advantages of simple structure,low power consumption,and facilitated integration.The power consumption source of SAR ADC is divided into three parts:DAC capacitor array,digital control logic and comparator.With the target of designing a 10bit 200KSPS ultra low power consumption SAR ADC,optimization methods for reducing power consumption is proposed from the two aspects of the comparator and the DAC capacitor array in this paper.Based on the application requirements of 10bit ultra low power SAR ADC,this paper proposed a calibration technology based on binary capacitor DAC.A low-power high-precision dynamic comparator is completed using 65nm CMOS technology.The simulation results based on layout show that our scheme can reduce the offset less than 0.25mV under 1.2V supply.It achieves a 0.33?W power dissipation while increase the 57%compared with the comparator without calibration.The overhead is worth while the power consumption is slightly.In addition,this paper presented a two-stage capacitor switching procedure with error compensation method.Two 10bit,200KS/s SAR ADCs are implemented in 65nm CMOS process.The one uses Switchback switch method,the other one uses two-step capacitor switching procedure.Comparing the performance of the ADCs with the simulation results based on layout data.The simulation results show that the power consumption can be reduced by 35.6%while the effective number is reduced by 1.7%,which indicates that the two-stage capacitor switching with error compensation mechanism can effectively reduce the overall power consumption of SAR ADC with guaranteeing the performance such as ENOB(Effective Number of Bits).