Hardware Design Of Quadratic Residues Based Low Cost RFID Authentication Protocol And Its FPGA Implementation

RFID is an automatic identification technology by non-contact two-way communication mode,which is used to achieve the identification of objects in Internet of things.RFID technology can accurately,quickly and real-time acquire and process the object information.So this technology is known as an upgraded version of bar code.However,RFID technology has a lot of advantages compared to bar code,such as high temperature resistence,long range,big storage capacity,anti-magnetic,waterproof and so on.In view of the above advantages,it is widely used in medical,tracking,positioning,retail and other fields,especially the low-cost RFID tags has been widely used in product tracking,baggage tracking,access control and inventory control.As the communication between the tag and reader use wireless radio channel,it is easy for the adversary to attack and tamper with the transmitting information.Therefore,the research on RFID authentication is very important.Currently the public key RIFD authentication is a hot topic because of its flexible key management.But traditional public key cryptosystem has high computing complexity,which does not satisfy the low cost requirement,therefore it is imperative to optimize the public key RFID authentication and the hardware structure of public key operation.In this thesis the above problem is deeply researched,and the following results are obtained.A quadratic residue based low Hamming weight low-cost RFID authentication protocol is reseatched.Considering the secure requirement,low cost and hardware resource assumption,we improve the authentication protocol under the condition of security.In this protocol,the quadratic residue based low Hamming weight one way function and modular n operation are improved,which greatly reduces the public key computing complexity.Then the hardware structure for the operations in the tags is designed,including 3x3 multiplier and 1024 bit multiplier.In the design,the computing speed is increased as far as possible under the condition of low resource assumption.Finally,the scheme is simulated in FPGA platform.The results show that the equivalent logic gates is 4688,which satisfies the low cost RFID authentication requirement.