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Research On Jitter Noise In High-speed Sampling System

Posted on:2015-08-20Degree:MasterType:Thesis
Country:ChinaCandidate:C WangFull Text:PDF
GTID:2348330518972580Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In modern communication and radar applications, the sampling system is a key part of changing analog signals into digital signals. The effects of jitter noise come out with the increase of sampling rate and input signal frequency in sampling system. Due to exist of jitter noise in high-speed sampling system, the noise floor of sampling system is significantly elevated, and it leads to the decrease of system output signal-to-noise ratio, it even limits the dynamic range of many digital receivers. Therefore, the further research of jitter noise in high-speed sampling system has important significance.The main contents and work of this paper are as follows:Firstly, it introduces the basic principles and main performances of ADC, and it analyzes different noise conditions and noise characteristics in sampling system. The jitter and jitter noise models is established respectively based on introduces of the production, definition and classification etc. related theory.Secondly, in order to determine the value of jitter time in high-speed sampling system, it improves the method of determine the jitter using the value of phase noise, and it also discusses the method of obtain the total jitter time by measuring output signal-to-noise ratio of the system. After determining the value of jitter, further study its effects on output signal-to-noise ratio of high-speed sampling system, and it comparative analyses the restrictions on output SNR due to different noises.Finally, according to the above theoretical basis, this topic designs and development a high-speed sampling system based on FPGA to conduct some verifying test. The accuracy of two methods of determine the jitter is verified through experimental analysis; each noise limit on the system output signal-to-noise ratio is obtained by the actual high-speed sampling system; and it puts forward we can forecasting the achieved output signal-to-noise ratio index in high-speed sampling system by drawing the output signal-to-noise ratio curve impact by different noise after theoretical studies; also the paper puts forward some select suggestions of related devices and the method to set related parameters in high-speed sampling system.
Keywords/Search Tags:Jitter, High-speed sampling system, Noise, Signal-to-noise ratio, FPGA
PDF Full Text Request
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