Research On UVM Verification For Audio Front End

The design and verification of smart phone chip is becoming increasingly complex with the growing of smart phone chip and the diversity of the smart phone function.As a common component of a mobile device,the audio front end module provides the user with the audio device interface and performs the digital to analog conversion,filtering and caching of the audio data.The correct design and verification of the audio front end module is the prerequisite to ensure the basic and normal operation of the smart phone,especially,the correct transmission of the data stream,between the audio front end module and the main chip is the basis for ensuring the correct function of the smart phone.This paper uses the current mainstream UVM verification method to replace the direct test method in previous project to complete the audio front-end module top-level verification work.By the analysis of the audio front-end module specification and the advanced feature list provided by the concept engineer,the function points of the module are extracted and a detailed list of verification is made.After that,the test platform of the module is completed by using the UVM verification method,Based on the verification platform,the EDA simulation tool is used to run the debug test case,which covered the list of validated features.In this paper,the functional architecture of the audio front-end module is analyzed,and the structure of the two data paths of the module is introduced,including the microphone channel and the audio input direction consisting of headphone,earpiece and loudspeaker channel.This paper focuses on the transmission protocol of the I2 S which is the interface component to connect audio front end with external chip together.Verification objectives are extracted after verification engineers comprehending the specification.This paper design and complete the audio front end verification platform according to the UVM platform architecture,and the detail method of each platform component is introduced.This paper completes the data encapsulation,validates the platform component creation and connection,builds testcase for the design and extracts the result efficiently and quickly according to the architecture of UVM platform.This paper debugs a large number of testcases via using Modelsim simulation tool.During the simulation process,this paper analyzes the typical waveform obtained by the monitor component in UVM platform.The result of the simulation indicates that the function coverage has already reached 100%,which meet the demand of the project and ensure the efficiency and reusability as well.The result indicates that it is not only more efficient and convenient to use UVM verification platform to run testcases,but also more conducive to follow-up the project succession.