The Design Of Fast Settling PLL Frequency Synthesizer Based On ADF4193

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters.The switching architecture ensures that the PLL settles inside the demanded time slot guard period,removing the need for a second PLL and associated isolation switches.This decreases cost,complexity,PCB area,shielding.This paper realized a kind of PLL circuit based ADF4193,in order to generate a signal from 1640 to 1900MHz,and the frequency fast settling within 30us.In circuit design,firstly I select VCO and filters according to the specification such as frequency?output power?phase noise and hopping time.And determine the power scheme on the basis of active component,while selecting the power chip.Lastly I design the parameter of loop filter and write the program of configuration register,using of SimPLL and ADF4193/6.After the chip model is determined,I design schematics by using CADENCE ALLEGRO,then draw the PCB layout with the same software.PCB drawing is send to the PCB making factory for producing circuit and mounting component.When the circuit is realized,the important parameters is need to measure by some experiment instrument,and I find the key problem for debugging circuit and optimizing performance,by making change in loop filter bandwidth?attenuation value and input or output match circuit.A phase lock loop(PLL)circuit based ADF4193 is designed and achieved in this thesis,there is a significant improvement in frequency lock time,which not worsen the performance of phase noise or frequency stability.The designed circuit is further optimized and analyzed according to the software simulation result.