The Design Of Intelligent Two-wire Instrument Dedicated Chip Which Support HART Protocol

HART protocol is the most widely used in industrial field bus communication protocol currently,it is based on the traditional two-wire transmitter.The two-wire instrument is also known as loop power supply instrument,only two wires are used to connecting the instruments and the control room,they are both power line and signal line,4-20 mA loop current is the signal corresponded with the measured physical signals.HART protocol is a kind of digital communication protocol that achieved by superimposing digital signal on 4-20 mA analog signal to achieve digital in the style of FSK,this digital communication is currently used for on-site calibration of the instrument.Two-wire instrumentation circuit usually needs dedicated chip designing.The chip discussed in this paper is to achieve the two-wire instrument function and support the HART protocol,but it now has no stereotypes product.This paper introduces a two-wire instrument-specific chip designed with domestic process,and focuses on discussing the design and implementation of modulation circuit and demodulation circuit.This design extends the function of the original chip by increasing the modulation and demodulation circuit,based on a completed two-wire instrument chip which uses domestic process.The technical difficulty of the subject lies in the chip area and power consumption,simply integrating the circuits of the two chips can lead to excessive area and excessive power consumption.The main innovation of the paper is to propose a new modulation circuit design method,the design uses a technology of waveform synthesis to achieve the sine wave signal,and the current control method to solve the FSK signal frequency control problem.The chip area and the distortion of the output signal waveform is reduced by comparing with the traditional method.Switched capacitor filtering technology is used to reduce the chip external components and special digital circuit is used to identify the received signal in the demodulation circuit,so the chip area and the power consumption are reduced.This design is achieved based on the domestic BCD process,the correctness of the circuit is verified through rigorous simulation analysis.First of all,the design uses Cadence software to design each functional module,and then uses HSPICE to simulate the various modules mainly including waveform generation circuit,comparator,operational amplifier,switched capacitor filter and digital control circuit.Finally,the Hua Hong NEC BCD 0.35?mGE process is used for layout drawing and the design has passed the DRC and LVS check rules.