Research And Hardware Design Of Polar Coding And Decoding Algorithm

Channel coding technology can improve the quality and increase the capacity of communication systems remarkably,therefore communication researchers are always searching for a channel coding algorithm that is able to achieve Shannon limit.In 2007,a significant coding method called Polar Code was proposed by professor E.Arikan.It can be theoretically proved that the coding method can achieve Shannon limit in binary discrete memory-less channels at the expense of low level computation complexity.As a burgeoning channel coding method,polar code has attracted wide attention of academia and become to one of the most popular research areas of communication.In 2016,polar code was confirmed to be the standard coding method of control channel in next generation wireless communication system(5G),which made the research and hardware design of the polar code gains great significance.This paper first researched and analyzed the polar coding and SC decoding algorithm,then mainly focused on developing the hardware structure of polar coder and decoder.In the process of developing SC decoder,this paper proposed a hardware structure to recursively compute log-likelihood ratio(LLR)for meeting the practical requirements,which is able to achieve functions of decoder only consuming less hardware resource.After completing the design of whole system,we have successfully synthesized the of polar coder and decoder implemented by Verilog HDL utilizing QuartusII software,got the RTL circuits and the information of hardware costs of them.In addition,we designed a simulated communication system under BAWGN channel by combining the Modelsim and Matlab software to test the whole design.From the results of the simulation,we drew a conclusion that the hardware implementation of polar coder and decoder designed in this paper are reliable.