Design Of RF Front-End Integrated Circuits For Compressive Sensing Receiver

With the rapid development of wireless communication technology,communication terminals should be capable of supporting a variety of standards,which need a wideband receiver.Compressive sensing(CS)receiver is a kind of wideband receiver structure.The local oscillator(LO)pseudo-random sequence has the characteristic of wideband discrete spectrum.The sparse RF signals distributed among a wide frequency band can be relocated to the low-pass band and be linear aliased,for the purpose of recovering the original signals.To cover the sub-3 GHz RF signals,the speed of the LO sequence should be as high as 6 Gbps.Conventional high speed random sequence LO of the CS receiver costs too high in the hardware circuits.To avoid this drawback,this thesis improves the mixing method of the CS receiver.It uses multiple low-speed-sequences mixing instead of the high-speed mixing structure,and it greatly reduces the cost of the hardware system.My researches are focus on the design of RF front-end of the CS receiver,including LNA,mixer and other auxiliary circuits.Through the theoretical analysis and simulation verification,the design of RF frond-end of the CS receiver is implemented based on 0.13 μm RF CMOS process.The major contents can be summarized as follows:Firstly,this thesis proposes a low-speed-sequences mixing method,which reduces the LO rate of the CS receiver.The key issue of a CS receiver is to generate wideband discrete spectrum.In order to replace the high-speed-sequence mixing,an alternative technique of multi-stage low-speed mixing is proposed.We use three low-speedsequences mixing stages instead of high-speed mixing.It can be achieved by three synchronized sequences of different speed or three time-delayed sequences of the same speed.Compared to the high speed mixing,the low-speed mixing structure achieves comparable IF output spectrum density,whose correlation coefficient of the sensed matrix just deteriorate about 0.1.Secondly,in order to meet the bandwidth requirement,the inductor peaking technique is summarized and analyzed.We analyze the methods of bandwidth extension for LNA.Based on the above methods,the author designs a two-stage balanced wideband LNA,which achieves 0.4-9 GHz bandwidth,3.7-5 dB noise figure and-3 dBm IIP3,but two large inductors are used.In order to reduce the noise figure,we design another LNA.It adopts noise cancelling technology to reduce the common mode noise of the common gate and common source amplifier.The noise figure of this LNA is about 3 dB,the bandwidth is 0.3-7.5 GHz,but three inductors are used.The former two LNAs cost too many chip areas.We design a resistance-feedback LNA which uses only a small gate-peaking inductor to obtain the bandwidth from DC to 8 GHz.The noise figure is 3.5 dB,the IIP3 is-7 dBm.Comparing the above three kinds of LNA,under the condition of equal basic performance,the third one occupy smaller area.So it is chosen for the RF frond-end.Thirdly,to meet the demand of multiple low-speed-sequences mixing,the author designs a double-balanced active mixer considering receiver chain performance.In order to improve the isolation from the LO port to the LNA’s RF port,we change the common source RF amplifier stage to the cascode topology.It blocks large LO signal leakage to the RF port.Furthermore,we design complete cascade circuits including the LO and output buffers.After the chip layout design,we finish the post simulation.The result shows this receiver can cover 0.8-6 GHz RF band,the output P1 dB is greater than-12 dBm,the IF output has a strong power distribution at low frequency.Finally,the chip is taped out and tested.We design two kinds of test methods.The basic function is tested under the single tone LO.The mixing function is tested under the low-speed-sequence LO.The RF front-end circuits are mounted by COB package.We design two test circuits,build a test system and analysis the test results.Sequence mixing test shows a gain of up to 13 dB at 100 MHz IF output,and up to 8.7 dB attenuation.IF output has a strong power distribution at low frequency.After time domain comparison,the wideband modulation signal test indicates that the chip can achieve the basic functions.