The Architecture Research And Critical Circuit Design Of 12 Bit High-speed A/D Converter

The rapid development of wireless communication, radar and software radio technology has set a higher requirement of A/D converter nearly as RF,requiring not only an ultra-high speed sampling rate, but also a higher conversion accuracy. In a variety of high-speed A/D converters, the folded and interpolated ADC(analog-to-digital converter) has a conversion rate comparable to that of a fully parallel ADC, with less area and lower power consumption,while its accuracy can be further improved. In view of the above advantages of folded and interpolated ADC, this dissertation has carried on the research in the system architecture level.The dissertation first introduces the basic principles of ADC and the main technical specification, and secondly, it analyzes the structure of a variety of A/D converters, weighing their pros and cons. Then, the various non-ideal factors that may exist in the actual folded and interpolated converter are analyzed in detail. The working mechanism of two key circuits---preamplifier and cascade folder is analyzed, and the circuit structure and performance are optimized. The simulation verification is carried out to ensure the realization of the design goal. Cadence Spectre shows that the bandwidth of the pre-amplifier is 2.761GHz and the gain is 11.85dB. With a larger gain, the input offset can be inhibited. Cascade folder can achieve a two-stage folding with a 2.4GHz bandwidth. In addition, in order to push the limits of the speed and precision of traditional folded and interpolated architecture, this dissertation improves the traditional folded and interpolated ADC architecture with interstage pipelining and cascade folding technique---The cascade folder can be less intervened by the multiplier effect; the interstage pipelining technique allows a faster response in the conversion path, and thus the conversion speed also increases. This dissertation designs a cascade folded and interpolated scheme with a folding coefficient of 3 and an interpolating coefficient of 3. 27 pre-amplifiers and 6 stages are used to complete the high-speed folded and interpolated ADC with a resolution of 12 bit architecture design.In order to verify the feasibility of cascade folded and interpolated architecture, the whole Verilog-A behavioral model of 12bit high speed folded and interpolated ADC is built on Cadence Spectre simulation platform. The results of behavioral simulation show that the effective number of bits (ENOB)of the converter reaches 11.58bit when the sampling frequency is 500MHz and the input signal frequency is 244.14MHz, which fully verifies that the interstage pipelining technique and cascade folding is important to improve the speed and precision of the converter.