Optimization Of Low Power Transceiver In Inductive Coupling Interconnection For Three-dimensional Stacked Chips

With the development of CMOS process node below 10 nm, Moore's Law has suffered serious challenge. Three-dimensional stacked package technology is paid more attention as a way to improve transistor integratio n level. Inductively coupled interconnection stands out because of advantages of its high reliability and low cost. Transceiver in inductive coupling inter-chip link is equivalently wireless interface. To improve the performance of inductive ly coupled interconnect channel, power consumption problem of the transceiver has to be solved.Firstly, the inductively coupled interconnect channel for three-dimensional stacked package is set up. One-coil relay transmission communication is proposed by replacing the conventional three-coil relay transmission communication and Ag glue slope stacking method is presented instead of bonding wire stacking method. Then, a variety of design methods of low power transceiver circuits are introduced for providing theoretical basis of proposed novel power optimized transceiver. And the equivalent model of Inductive coupling interconnection is in detail analyzed and discussed to acquire the calculation method of inductance value and coupling coefficient. Based on Greenhouse's calculation model and Asgaram's symmetric approximation model, the new calculation method is proposed for multilayer on-chip inductor. In the end, two kinds of low power transceiver, Current-steering structure and Single phase modulation technique, are designed combined with low power design method s. And measurement results reveal that inductively coupled wireless interconnect channel c an function well. Power consumption of transceiver with current-steering structure is 42 mW at a data rate of 2Gb/s per channel and bit error rate is 10-12. Power consumption of transceiver with single phase modulation structure is 1.25 mW with a 1Gb/s data rate and bit error rate is lower than 10-13.