Critical ALU path optimization and implementation in a BiCMOS process for gigahertz range processors

Binary addition is a simple ubiquitous component of computational circuits. One can hardly imagine a computer that did not add; to many it wouldn't even merit the name. In both general-purpose and application-specific processors the adder delay is a strong metric for cycle time.; This research spans three areas that contribute to adder speeds: logical arrangement of carry generation, circuits to implement that arrangement, and high-speed semiconductor devices to realize those circuits.; Carry generation belongs to a class of parallel computation problem knows as parallel prefixes. The basis of this work's logical design is pseudo-carry look-ahead, a method that uses tree-like structures to minimize gate depth on critical paths and trades delay from critical paths to non-critical paths.; The logical forms that reduce the serial computations necessary for addition are interrelated with the circuit forms that allow the fastest generation of those computations. Special circuits to compute look-ahead in a single gate reduce signal path length and allow driving of signals at high speeds.; Silicon Germanium HBTs provide high-speed devices while leveraging the mature lithography of traditional silicon processes. Not only can fast circuits be built, but high integration allows not just large units like adder but whole systems into which adders would be embedded.; The combination of these three areas has allowed the construction of a 32-bit pseudo-carry look-ahead circuit with a delay of 146 ps in a 50 GHz f_T SiGe process. In addition, direction for future work have been established that lead to delays on the order of 32 ps.