Research On Hardware Architecture Of AdaBoost Hand Detection Algorithm Based On FPGA

With the development and widespread application of image processing technology, a new generation of interactive human-computer interaction systems which are different from the traditional system, are developing rapidly. Gesture control system is a new kind of interactive systems applied more widely used. Currently at home and abroad, gesture control system has been trying to apply on a smart TV.Hand detection plays a very important role in gesture control applications. In the context of complex background, accurate and rapid hand detection affects the response speed and precision of gesture control system. At present, the gesture control system is not yet mature, both in speed and accuracy are also lacking. Accurate and rapid hand detection system has a significant role in promoting development. AdaBoost detection algorithm based on Haar features or LBP feature is one of the mature algorithm which has high detection rate currently applied to hand detection, it will correctly detect the hand in a complex background, but detection requires a lot of computation and high data throughput restricting its application. Therefore, in order to achieve the gesture control system for real-time response requirements, looking for detection algorithm hardware acceleration method is a hot subject at home and abroad. Using FPGA architectures to achieve is one viable optionBy studying AdaBoost hand detection algorithm, combined with FPGA parallel computing features, designing hardware architecture with high processing speeds to solve the large amount of computation and data throughput issues.This article focuses on the study of the theory of algorithms, the algorithm improvement, hardware architecture and system verification. The main work includes the following aspects: Firstly, the algorithm theory, including AdaBoost algorithm framework and a variety of features related to hand detection, combined with FPGA parallel pipeline operation characteristics, study the feasibility of implementation; secondly, according to the FPGA features and characteristics of the data flow algorithm, improving the algorithm work control process, so that it can adapt to the pipeline operation mode, and can give full play to the advantages of FPGA parallel computing; thirdly, according to the improved algorithm design the appropriate hardware architecture; fourthly, verify the system on the development platform, and compared the performance with others detection system.This design uses Verilog HDL hardware description language of the architecture of behavioral modeling, and to achieve functional verification on DE4 development platform which provided by Terasic. The design and implementation of real-time hand detection system, capable of a resolution of 640 × 480 images in real-time detection, the processing speed of 144 frames per second.