The Research Of Demodulation System Of 64QAM High Order Digital Modulation And Its Implementation With FPGA

In recent years, software radio, also called software defined radio technology has become an important architecture in the field of communication. Software radio is achieved through software to implement the hardware design of communication system, of which Field Programming Gate Array(FPGA) technology is an available means. Based on software radio,a communication system can be adapt to a variety of communication methods and has good flexibility, compatibility and programmability. As an advanced technology method, FPGA technology not only owns rich hardware resources but also owns unique hardware description language to module functions of each part and has good readability for user-friendly modification. However, not all algorithms are suitable for hardware implementation in real project implementation process. Therefore, it is necessary to study, optimize and validate the modulation and demodulation algorithms in communication systems. The subject comes from the study of FPGA for high order digital modulation and demodulation system, which is supported by the Broadband Wireless Communication Laboratory of the Research Institute of Tsinghua university in Shenzhen. Based on the FPGA platform for high order digital modulation and demodulation system of 64 Quadrature Amplitude Modulation(64QAM), this paper mainly studies about carrier synchronization, timing synchronization and soft demodulation algorithms in 64 QAM digital communication system. Main efforts of this thesis are as follows:1) By studying soft information calculation methods for 64 QAM modulation and demodulation techniques by the means of Matlab software platform, the Log Likelihood Ratio(LLR) calculation of soft information algorithm has been improved based on FPGA implementation, which reduces the complexity of the LLR algorithm and hardware resources usage. The results show that, compared with traditional method of soft information calculation, the improved algorithm in this paper requires only a smaller number of comparisons and additions without the use of a multiplier, thus saving the cost of hardware resources.2) Synchronization methods are studied and Matlab simulations are made. Then,the FPGA is used to achieve the Costas loop of carrier synchronization and Gardner algorithm of timing synchronization. On the basis of these two loops and the principle of automatic adjustment of phase locked loop, a power gain control loop is completed in the demodulation system, making the system achieve a stable power gain to further reduce the bit error rate caused by Inter-Symbol Interference(ISI) or low power. Then, simulink tools are adopted to build a 64 QAM demodulation system with automatic gain control.3) The verilog hardware description language is applied to realize the demodulation algorithms of 64 QAM signals on the Xilinx's FPGA. And combined with PC debugging platform, network analyzer, spectrum analyzer and other equipment, the error bit rate of the64 QAM demodulation system is tested, so that the practicality and performance of the algorithms are verified on the FPGA platform which is for high order digital modulation and demodulation system.