Design And Implementation Of Uncooled Lwir Imaging Processing System

No matter in the field of military, commercial and civil fields, infrared image processing system has been widely used, with small size, low power consumption, processing performance features to enhance the degree of concern on the infrared imaging technology around the world. Uncooled long-wave infrared image processing system designed in this paper, not only has the above characteristics of infrared imaging systems, but also has the ability to handle complex image algorithms. The system uses FPGA and DSP processor as the core of the system operation to achieve the infrared imaging, image acquisition, non-uniformity correction, histogram equalization and image transmission with the host computer. The main research results are as follows:According to the system design requirements, the infrared image processing system is divided into four parts: long-wave infrared detector plate, FPGA image preprocessing board, DSP image algorithm board and an external interface board. The overall system uses the physical structure of four boards stacked, connected by high-speed inter-board connector. Detecting core system use ul04371 detector. According to the actual needs of the system selected altera's cycloneIII series FPGA as a pretreatment board processor. System selected TI's high-performance DSP processor TMS320C6657 algorithm as an image core processor. This image processing system has the characteristics of strong image processing performance, low power consumption, small size and low cost.In order to solve the problem of nonuniformity of infrared image, this paper studies the nonuniformity correction algorithm of infrared image.An improved type RAM array with external memory caching mechanism, by using this unit achieve a two-point calibration correction algorithm. By writing logic within the processor in the FPGA design implement a set of non-uniformity correction image process. A set of logic control unit is designed to coordinate and manage the work of each logic module. In order to make the system have the function of contrast enhancement, the histogram equalization module is established by compiling the logic in the system. The histogram statistics and histogram equalization are realized in this system. In order to reduce the complexity of the histogram equalization operation and reduce use module hardware resources.In this paper, using the register array to achieve statistical histogram, avoid the traditional methods in the decoder and multiplexer to bring the problem of high complexity. At the same time, the dual port ram as mapping lookup table, reduces the computational complexity.In order to achieve communication with the host computer, DSP / BIOS operating system is established in the DSP processor, through the operating system to create interface interrupt threads and Ethernet task threads.Implements task thread scheduling, in conjunction with DDR3 external memory algorithms board completed the task of storing and reading image preprocessing.The image transmission and instruction interaction of the FPGA processor is realized through UPP interface and the serial port logic. NIOSII chip programmable processor is embedded in the FPGA chip. FPGA processor configure infrared detector, and control ADC chip and parallel to serial conversion chip to realize the function of image acquisition and serial image data recovery for parallel image data on image pre processing.