Hardware Circuit Design Of MIMO Detection Algorithm In LTE/LTE-A System

MIMO technology can improve the system throughput and spectrum efficiency without increasing the system bandwidth since it makes full use of the spatial characteristics of the channel. But it also increase the difficulty of signal detection. With the increase of the antennas number and modulation, the complexity of MIMO detection algorithm is increased, and the hardware implementation of MIMO detection require more and more flexible.Therefore, the design of high performance, low complexity of reconfigurable MIMO detector is one of the current research hotspots.Based on the selection of the MIMO detection algorithms and analysis of existing research project, this thesis designs a high throughput, high BER performance and reconfigurable MIMO detector. The main research points are as follows:(1) Analysis of the current MIMO detection algorithm andconsidering the factors in the computational complexity, performance, flexibility and hardware realization method and finally this thesis selects the K-best detection algorithm as the hardware implementation algorithm; (2) According to analysis the principles and computational procedure of K-best detection algorithm, the main feature of the core operator in K-best detection are extracted. After the realization way of the core operator is optimized, this thesis designs a high throughputreconfigurable MIMO detector architecture; (3) Design the hardware of the proposed K-best detector. Focusing on the critical path of the PED calculation module and the basic multiplication and square operation, further simplification and optimization is conducted to resulting in the reduction of the system delay and the hardware cost. The reconfigurable design for the interconnection of the sorting module, which enables the detector to support a variety of different parameter configurations.In addition, Matlab is adopted to do floating-point and fixed-point simulation on K-best detection algorithm to determine the appropriate fixed-point structure. After that, this thesis uses Modelsim to do function simulation for the K-best Verilog HDL, and finally implementation on the Cyclone IV. Experiment results show that the K-best detector designed in this thesis is suitable for 2×2 to 4×4 antenna configuration, support the QPSK,16-QAM and 64-QAM modulation methods. The K value supports arbitrary integer between 1 and 8. Under the conditions of 4×4,64-QAM and K=8, the detector's throughput reached 2.88Gbps. The performance increases by 5 times while the area only increases 50%, comparing to the mainstream K-best hardware structure, while also supporting the reconfigurable parameters. The MIMO detector designed in this thesis fully meets the requirements of LTE/LTE-A system, and has advantages in throughput and flexibility.