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Design Of Multi-mode Multi-standard Receiver RF Front-End Resilient To Out-of-Band Blockers

Posted on:2017-01-03Degree:MasterType:Thesis
Country:ChinaCandidate:S P WangFull Text:PDF
GTID:2348330491962551Subject:Electronic and communication engineering
Abstract/Summary:PDF Full Text Request
In the future space environment, the wide coexistence of multi-mode multi-standard multi-band wireless communication systems will be an important trend in the development of wireless communications technology. A single-chip integrated of multiple wireless communication system has broad application prospects. Therefore, RF transceiver that supports multi-mode multi-standard becomes the research focus. However, the function of resilient to out-of-band blockers has been one of the bottlenecks in wideband multi-mode multi-standard receiver design, this paper will focus on RF front-end research and design in the blocker-tolerant receiver.Implemented in TSMC 0.18?m RF CMOS process, a blocker-tolerant RF front-end, including wideband low noise amplifier and impedance transfer network, is presented in this thesis. This RF front-end is applied to multi-mode multi-standard RF receiver. The proposed LNA employs capacitive cross-coupled common-gate structure. Based on passive mixer, the impedance transfer network accomplishes high Q value filtering by moving the baseband impedance to the RF band. The wideband LNA is working with a 3V supply voltage, its working frequency band covers 0.6GHz?2.8GHz. In this band, the S11 is less than -18.0dB, S21 is greater than 18.2dB, noise figure is less than 2.9dB, IIP3 is-0.55dBm,OIP3 is 18.14dBm.The blocker-tolerant feature of the RF front-end can be adjusted by editing capacitor array control word. When set to the narrowest IF bandwidth, the zero-IF signal around 2.4GHz has a voltage gain greater than 17dB, the blocker at 20MHz offset has a gain of about 3dB, the inhibition for blocker is greater than 14dB. The chip size is 0.66mm×0.58mm. The circuit consumes 10.8mW power excluding the output buffer, the output buff circuit consumes 30.6mW power. The post-simulation results show that the circuit has significant blocker-tolerant feature and meets the design specifications.
Keywords/Search Tags:Blocker-tolerant, wideband, LNA, capacitive cross-coupled, passive mixer, impedance transfer
PDF Full Text Request
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