Design Of Double-Basis Reconfigurable ECC System Over Binary Field Based On FPGA

With the development of information technology and the process of Internet of things gradually speeding up, information security becomes more and more important. ECC can provide greater safety at the same key length, so it has certain advantages compared with the RSA algorithm in the field of cryptography chip. Presently ECC cryptosystem hardware is mainly implemented by single interface and single basis representation. The ECC system based on double basis over binary field is studied in this paper and completed the FPGA hardware design of this system with the method of reconfigurable hardware design.In this paper, the design of double-basis reconfigurable ECC system over binary field based on FPGA, selected the K-233 and K-409 security curves recommended by NIST to implement the point multiplications. Firstly, this paper introduces the relevant theoretical basis of elliptic curve algorithm. Secondly, it puts forward the algorithm architecture of double-basis reconfigurable ECC system over binary field. Thirdly, the Hardware architecture is proposed, then the function modules are divided and each module has a RTL implementation. The point multiplication uses Montgomery multiplication algorithm under standard projection coordinates, and realized with master-slave state machine controling the finite field arithmetic units. This system realizes parallel operations of 3 reconfigurable modular multiplications and 3 modular inversions to optimize algorithm steps. Lastly, the ECDSA application protocol is implemented based on the double-basis reconfigurable ECC system.In this paper, Verilog HDL language is used for RTL design and Modelsim is used for front end simulation. Then the FPGA verification is completed by Virtex-6 development board. The functional correctness of this system is proved in verification process and it can support the generation and verification of ECDSA. This design reached the requirements of each width. The operating frequency of the hardware circuit can be up to 211.93MHz.